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Mechanism to CHECK Data Integrity in a Serial Link Transmissions Working With LSSD Strings

IP.com Disclosure Number: IPCOM000042923D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Lechaczynski, M: AUTHOR [+2]

Abstract

This article relates to the checking of data serially transmitted between different parts of an information-handling system designed with Level Sensitive Scan Design (LSSD) logic circuits. The checking is made by using the existing system hardware which prevents costly cyclic redundancy checking circuits from being incorporated in the system. In the drawing, a serial LSSD link which allows the data bits to be transmitted between a Service Processor (SP) and a Central Processing Unit (CPU) is schematically represented. The data serialized in the SERDES (Serilizer-Deserializer) register in the Service Processor (SP) are transmitted to the CPU through the B0 and B1 registers. Parity Generators (PGs) are associated with each register. The checking operation comprises three steps.

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Mechanism to CHECK Data Integrity in a Serial Link Transmissions Working With LSSD Strings

This article relates to the checking of data serially transmitted between different parts of an information-handling system designed with Level Sensitive Scan Design (LSSD) logic circuits. The checking is made by using the existing system hardware which prevents costly cyclic redundancy checking circuits from being incorporated in the system. In the drawing, a serial LSSD link which allows the data bits to be transmitted between a Service Processor (SP) and a Central Processing Unit (CPU) is schematically represented. The data serialized in the SERDES (Serilizer-Deserializer) register in the Service Processor (SP) are transmitted to the CPU through the B0 and B1 registers. Parity Generators (PGs) are associated with each register. The checking operation comprises three steps. During the first step, the parity of the byte to be received from B1, for instance, is latched in Latch 1. During the second step, the bit shifting occurs as follows: During the third step, the parity of the new contents c of SERDES is compared with the parity latched in Latch 1. An equality indicates that no error has occurred in the transmission from B1 to SERDES and, in case of a parity check, the indication CHECK RCV is latched in latch 4. The parity of the new contents a of BO is compared with the SERDES old parity latched in Latch 2. An equality indicates that no error has occurred in the transmi...