Browse Prior Art Database

Hardware Dynamic Multiplex

IP.com Disclosure Number: IPCOM000042925D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Callens, P: AUTHOR [+3]

Abstract

The purpose of this system is to multiplex two SDLC (Synchronous Data Link Control) lines (one having highest priority) on one physical line. Each SDLC link can work at the maximum rate of the line (RM). When the priority SDLC link is working at a rate R, the lowest priority SDLC link works at (RM-R). The hardware adapter is transparent to the Data Terminal Equipment (DTE). In conventional SDLC, fixed frames of bits are transmitted. Each frame starts with a one-byte long opening flag (F) field followed by an address field (A), also one byte long. Then come a control field (C), followed by an information or data field and a frame check sequence (FCS) field (2 bytes long). And finally, the frame ends with a closing flag (F). Both flags are similarly equal to the 7E byte in hexadecimal, i.e., 01111110.

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Hardware Dynamic Multiplex

The purpose of this system is to multiplex two SDLC (Synchronous Data Link Control) lines (one having highest priority) on one physical line. Each SDLC link can work at the maximum rate of the line (RM). When the priority SDLC link is working at a rate R, the lowest priority SDLC link works at (RM-R). The hardware adapter is transparent to the Data Terminal Equipment (DTE). In conventional SDLC, fixed frames of bits are transmitted. Each frame starts with a one-byte long opening flag (F) field followed by an address field (A), also one byte long. Then come a control field (C), followed by an information or data field and a frame check sequence (FCS) field (2 bytes long). And finally, the frame ends with a closing flag (F). Both flags are similarly equal to the 7E byte in hexadecimal,
i.e., 01111110. Whenever no data are provided to the transmitter, the latter repetitively transmits the flag F. Shown in the figure is very simple hardware which enables the multiplexing of the data provided by DTE 1 and DTE 2, with DTE 1 being assigned the higher priority. Distinguishing each terminal from the other is achieved by starting the DTE 1 address with a "1" bit while the DTE 2 address starts with a "0" bit. Consequently, the DTE 1 bits are provided to a 10- bit shift register, nine of which are decoded to detect the 011111101 pattern. Upon such a decoding, a gate A1 is opened to the DTE 1 bits while a gate A2 is closed to DTE 2. On the receiving...