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Latch-Up Free, Double-Gated, Enhancement-Type P-Channel Device for CMOS With Enhanced Transconductance

IP.com Disclosure Number: IPCOM000042927D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Ogura, S: AUTHOR [+2]

Abstract

The problem of latch-up is a well documented phenomenon. To avoid this this situation, a barrier to current flow is necessary so that N-channel source and drain junctions do not become forward biased as a result of the presence of holes. The approach to solving this problem presented here is to isolate the source of the holes (the P-channel device) using a buried insulator layer. The formation of this layer results from implanting, for example, nitrogen beneath the P-channel regions sometime after recess oxide isolation (ROX) formation and using heat treatment to cause the implanted nitrogen to react with the background silicon. The result is a localized, buried, controllable isolation layer of silicon nitride, as seen in Fig. 1.

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Latch-Up Free, Double-Gated, Enhancement-Type P-Channel Device for CMOS With Enhanced Transconductance

The problem of latch-up is a well documented phenomenon. To avoid this this situation, a barrier to current flow is necessary so that N-channel source and drain junctions do not become forward biased as a result of the presence of holes. The approach to solving this problem presented here is to isolate the source of the holes (the P-channel device) using a buried insulator layer. The formation of this layer results from implanting, for example, nitrogen beneath the P-channel regions sometime after recess oxide isolation (ROX) formation and using heat treatment to cause the implanted nitrogen to react with the background silicon. The result is a localized, buried, controllable isolation layer of silicon nitride, as seen in Fig. 1. A mask is added to the conventional N MOS process to allow nitrogen to be implanted only in the P-channel areas. Only 100 A of silicon nitride are needed to block the flow of holes. Shown in Fig. 1 is a cross-section of an area with both P and N-channel devices, after the nitrogen (N2) implant. In such a CMOS process which uses P-type substrates, an N-type well normally is formed. In this well the P-channel device is fabricated. In the new device presented here, no N-well is formed. The isolation afforded by reverse biasing the N-well is now provided by the buried silicon nitride layer 16. However, besides this novelty, the P-channel device disclosed here is fundamentally different in operation from the conventional P-channel device used in CMOS. A thin N-region or "N skin" is formed inside the buried silicon nitride layer by implanting phosphorus (P) at the time the nitrogen implant is performed, as seen in Fig. 2. The gate material is N+ polysilicon. Since this is also the gate material of the N-channel device, the polysilicon can be implanted or otherwise doped N-type, such as by POCl3, before it is patterned and then the blanket polysilicon layer can be etched. The process may be understood with reference to the figures. It starts by the use of the usual ROX technique to achieve local oxidation of monocrystalline silicon surface regions 10; but after Si3N4 removal, for example, by hot H3PO4, the pad SiO2 layer 12 is left on. Polysilicon layer 14 is deposited thereover. A resist 15 mask is used to etch the polysilicon and to mask the N2 implant that will form the thin silicon nitride (Si3N4) layer 16 for P- channel device isolation, as seen in Fig. 1. Now the resist mask 15 is stripped, and the Si3N4 layer 16 is formed by an anneal at 1000OEC for 90 minutes. Next, the "N skin" 18 is formed by implanting doubly-ionized phosphorus (P) at 180 keV at 1x1012 dose. The polysilicon layer 14 acts as a mask over the planned N-channel device to form the resulting Fig. 2 structure. The polysilicon layer 14 is etched off, the pad SiO2 layer 12 is removed, and the gate silicon dioxide layer 20 is grown. A "buried...