Browse Prior Art Database

Mapping and Memory Hardware for Writing Rectangles and Horizontal Lines

IP.com Disclosure Number: IPCOM000042930D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Burroughs, SH: AUTHOR [+2]

Abstract

This article describes a mapping for storing an array in 64K memory chips, and the required data transformations, address calculations, and chip hardware. As described, the mapping and hardware provide bit addressability in both horizontal and vertical directions. However, removal of the incrementer associated with the word and/or bit address will remove the bit addressability in the vertical and/or horizontal direction, respectively, while still retaining the ability to write 16 bits horizontally beginning at an even byte boundary and 4x4 blocks beginning at even byte boundaries horizontally and half-byte boundaries vertically. Fig. 1a and 1b show the mapping of the array into the memory chips.

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Mapping and Memory Hardware for Writing Rectangles and Horizontal Lines

This article describes a mapping for storing an array in 64K memory chips, and the required data transformations, address calculations, and chip hardware. As described, the mapping and hardware provide bit addressability in both horizontal and vertical directions. However, removal of the incrementer associated with the word and/or bit address will remove the bit addressability in the vertical and/or horizontal direction, respectively, while still retaining the ability to write 16 bits horizontally beginning at an even byte boundary and 4x4 blocks beginning at even byte boundaries horizontally and half-byte boundaries vertically. Fig. 1a and 1b show the mapping of the array into the memory chips. It is seen that 16 horizontal bits are placed into corresponding locations in each chip with a bit increment for those chips associated with bits crossing an even byte boundary. The mapping of a 4x4 block is somewhat more complicated, in that the bits of each of the 4 horizontal slices are placed in a different quadrant of a word. The word address increases by 1 when the quadrant becomes 0. The important observation to be made about the mapping is that 16 horizontal or a 4x4 block of bits can be written into memory in one cycle because no two bits are mapped to the same chip. Given that these bits can be mapped into the memory in one write cycle, the next important question is the computational complexity and the amount of additional hardware required. This complexity and hardware are required for address calculation and data manipulation, on-chip address translation, and memory to raster scan conversion. Address Calculation and Data Manip Horizontal Mode: The functions to be performed by the address generation chip are given by the following equations: Bit-address(5,4,3,2,1,0) = integer of X/16 or X(9,8,7,6,5,4) Bit-address(7,6) = 4 modulo Y or Y(1,0) Word- address(1,0) = 4 modulo integer of Y/4 or Y(3,2) Word-address(7,6,5,4,3,2) = integer of Y/16 or Y(9,8,7,6,5,4) Data = 16 modulo (X+4xY) rotate of 16 take Data Mask = 16 modulo (X+4xY) rotate of 16 take #Data 1's Bit-increment = 16 modulo (X+4xY) rotate of ((16-16 X)p0),(16 X)p1 Word-increment = 16p0 Mode = 0 Block Mode: The address of the first bit in the first horizontal line of the block is the same as that calculated in the horizontal mode. However, this bit is in chip 16 modulo (X+4xY). Since the add...