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Automatic Bit INDICATOR Generation

IP.com Disclosure Number: IPCOM000042935D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

delSol, PD: AUTHOR [+2]

Abstract

Improved performance of bit instructions is achieved. In some instructions for the IBM Series/1 processor, the Negative and Zero indicators are defined to have a special meaning different from the normal arithmetic meaning of these indicators for the rest of the instruction set. The instructions are Test Bit (TBT), Test Bit and Reset (TBTR), Test Bit and Set (TBTS), Test Bit and Invert (TBTV), and Test Word Immediate (TWI). For these instructions, the zero indicator is set if the tested bit or bits are all zeroes and the negative indicator is set if the tested bit or bits are all ones no matter what the rest of the bits in the word may be. This usually requires several microsteps to generate these indicators.

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Automatic Bit INDICATOR Generation

Improved performance of bit instructions is achieved. In some instructions for the IBM Series/1 processor, the Negative and Zero indicators are defined to have a special meaning different from the normal arithmetic meaning of these indicators for the rest of the instruction set. The instructions are Test Bit (TBT), Test Bit and Reset (TBTR), Test Bit and Set (TBTS), Test Bit and Invert (TBTV), and Test Word Immediate (TWI). For these instructions, the zero indicator is set if the tested bit or bits are all zeroes and the negative indicator is set if the tested bit or bits are all ones no matter what the rest of the bits in the word may be. This usually requires several microsteps to generate these indicators. For example, in the Series/1 Model 4955 processors, these indicators are generated for the bit instructions by first testing the bit and then generating a known dataword based on the bit test result which, when flushed through the ALU, will generate the correct indicators. For the TWI instruction an AND function is performed on the mask and data, and if the result is zero, the indicators are set and the instruction is finished. Otherwise, the result is exclusive-ORed with the mask, and if this result is zero, then a known dataword, which causes the Negative Indicator to be set, is flushed through the ALU for a total of three ALU operations. This identical function is performed on one cycle using the logic shown in Fig. 1 by...