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ALU MERGE Operation

IP.com Disclosure Number: IPCOM000042937D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+2]

Abstract

Increased speed and reduction of required hardware for a CPU are realized by incorporating a merge function into the design of the Arithmetic Logic Unit (ALU). Most ALU designs feature the capability to "AND", "OR", or to "XOR" two operands together. The ability to "ADD" and "SUBTRACT" is also included. Here, a capability is added to generate an additional function, called "MERGE". The "MERGE" function differs from previously implemented ALU functions in the following manner. A bit is selected from one of the two input operands and that selected bit becomes the resultant bit in the corresponding bit position of the output operand. In order to select the appropriate input operand from which to choose the bit, a third operand, called a mask, is necessary.

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ALU MERGE Operation

Increased speed and reduction of required hardware for a CPU are realized by incorporating a merge function into the design of the Arithmetic Logic Unit (ALU). Most ALU designs feature the capability to "AND", "OR", or to "XOR" two operands together. The ability to "ADD" and "SUBTRACT" is also included. Here, a capability is added to generate an additional function, called "MERGE". The "MERGE" function differs from previously implemented ALU functions in the following manner. A bit is selected from one of the two input operands and that selected bit becomes the resultant bit in the corresponding bit position of the output operand. In order to select the appropriate input operand from which to choose the bit, a third operand, called a mask, is necessary. If the mask bit is "ON", the corresponding bit from the A operand is chosen. If the mask bit is "OFF", the corresponding bit from the B operand is chosen. Previous implementations of merge operations require either multiple machine cycles, or a hardware merge mechanism that operates external to the ALU. This forces additional delay stages into the critical path. No additional delay stages are needed here, and much of the already available ALU circuitry is used. There are two areas of a typical ALU which are changed to accommodate the "MERGE" function. The carry generator is modified so that its output is controlled by the corresponding bit in the mask register while in "MERGE" mode. The sum generator is also modified so that its output when in "MERGE" mode reflects the status of the corresponding bit in either the A register or the B register depending on the output of the carry generator. Fig. 1 is a logic diagram of the carry generator for bit 1 of a 32-bit ALU. The circuitry shown below the dotted line has been added to accommodate the "MERGE" function. This circuitry when operating in "MERGE" mode produces a 1 on its output when the mask bit is "ON" and a 0 when the mask bit is "OFF". The circuitry above the dotted line performs the normal carry generation function and is disabled in "MERGE" mode. It should be realized that although 5 gates are shown below the dotted line, only 1...