Browse Prior Art Database

Improved Contact to a Shallow Semiconductor Region

IP.com Disclosure Number: IPCOM000042947D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Aboelfotoh, MO: AUTHOR [+2]

Abstract

This article describes a process for making a contact to a shallow semiconductor region, which results in improved stability of the contact resistance. Referring to the drawing, an N-type impurity, such as arsenic, is introduced into the P-type silicon substrate 10 by ion implantation to form an N+ region 12, which is isolated from other integrated circuit devices by the recessed oxide isolation regions 14. A silicon dioxide layer 16 is formed over the entire surface of the silicon substrate 10, including regions 14. A contact window 18, for providing interconnecting layers to be electrically connected to the N+ region 12, is then formed in the silicon dioxide layer 16 by conventional resist, lithography and etching techniques.

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Improved Contact to a Shallow Semiconductor Region

This article describes a process for making a contact to a shallow semiconductor region, which results in improved stability of the contact resistance. Referring to the drawing, an N-type impurity, such as arsenic, is introduced into the P-type silicon substrate 10 by ion implantation to form an N+ region 12, which is isolated from other integrated circuit devices by the recessed oxide isolation regions 14. A silicon dioxide layer 16 is formed over the entire surface of the silicon substrate 10, including regions 14. A contact window 18, for providing interconnecting layers to be electrically connected to the N+ region 12, is then formed in the silicon dioxide layer 16 by conventional resist, lithography and etching techniques. A polycrystalline silicon layer 20 is deposited over the silicon dioxide layer 16 and into the contact window 18 by chemical vapor deposition. The polycrystalline silicon layer 20 is then doped with an N- type impurity, such as phosphorous, by thermal diffusion or ion implantation. A layer of a resist material (not shown) is applied over the polycrystalline silicon layer 20 and standard lithographic and masking techniques are then utilized to provide a mask structure in the resist layer in areas lying directly above and slightly overlapping contact window 18 where silicon layer 20 is to be maintained. The polycrystalline silicon layer 20 is them removed using the resist layer as the mask, and is removed in undesired areas utilizin...