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Implementing Byte Instructions on a 16-Bit Processor With a Minimum Amount of Hardware by Right Justifying the Byte in a Field of Zeroes During ALU Operations

IP.com Disclosure Number: IPCOM000042958D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Fleurbaaij, JM: AUTHOR [+2]

Abstract

The above circuit shows how Main Store byte manipulation instructions are implemented on a 16-bit processor with only a minimum amount of hardware by always right justifying the byte in a field of zeroes as it is directed through the ALU for processing. The Main Store Output Buffer (MSOB) 1 consists of three 8-bit latch elements. When executing normal Main Store instructions, the new control line "MS Byte Instruction" 2 is not active, causing the AND gate 3 output "SWAP MSOB" to be inactive. Both the X and Y low and high byte enables 4 are active during normal Main Store instructions and the "SWAP ALU" 5 line is inactive. With this configuration full 16-bit data is gated through the Y-register and to the Y side of the ALU. With "SWAP ALU" inactive, the straight 16-bit ALU data is gated onto the System Data Out Bus.

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Implementing Byte Instructions on a 16-Bit Processor With a Minimum Amount of Hardware by Right Justifying the Byte in a Field of Zeroes During ALU Operations

The above circuit shows how Main Store byte manipulation instructions are implemented on a 16-bit processor with only a minimum amount of hardware by always right justifying the byte in a field of zeroes as it is directed through the ALU for processing. The Main Store Output Buffer (MSOB) 1 consists of three 8- bit latch elements. When executing normal Main Store instructions, the new control line "MS Byte Instruction" 2 is not active, causing the AND gate 3 output "SWAP MSOB" to be inactive. Both the X and Y low and high byte enables 4 are active during normal Main Store instructions and the "SWAP ALU" 5 line is inactive. With this configuration full 16-bit data is gated through the Y-register and to the Y side of the ALU. With "SWAP ALU" inactive, the straight 16-bit ALU data is gated onto the System Data Out Bus. When a byte instruction is executed, only 8 bits of information become significant. Bits 0-7 (referred to as the high byte) or bits 8-15 (referred to as the low byte). The control lines X High Byte Enable and Y High Byte Enable 4 are set inactive during the execution of these byte instructions, causing the outputs of bits 0-7 of the X and Y registers to be forced to zero. Two conditions can occur during the execution of byte instructions. One, the low byte of data from Main Store is desired, or two, the high byte of data is desired. The byte to be manipulated is determined by the clocking of the High/Low Byte flip-flop 6 during execution of the instruction itself. This latch...