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High-Speed Multi-Function Computer Clock Circuit With a Variable Frequency Output

IP.com Disclosure Number: IPCOM000042960D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Fleurbaaij, JM: AUTHOR [+2]

Abstract

This article describes a circuit which has the ability to vary the frequency of a computer's Master Clock to compensate for digital delays throughout the system. The clock circuit shown in the figure is used to generate a computer's Master Clock whose period can be varied from its nominal 25 megahertz frequency in 10 nanosecond increments. The circuit accomplishes this by using microcoded control input and its system circuits as feedback to start, stop, and/or block its phase clocks. The circuit shows 6 ways (indicated as (1) to (6) in the figure) to vary the Master Clock frequency: (1) The Stretch latch allows for micro-programmed switching of the Master Clock to one-half its frequency.

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High-Speed Multi-Function Computer Clock Circuit With a Variable Frequency Output

This article describes a circuit which has the ability to vary the frequency of a computer's Master Clock to compensate for digital delays throughout the system. The clock circuit shown in the figure is used to generate a computer's Master Clock whose period can be varied from its nominal 25 megahertz frequency in 10 nanosecond increments. The circuit accomplishes this by using microcoded control input and its system circuits as feedback to start, stop, and/or block its phase clocks. The circuit shows 6 ways (indicated as (1) to (6) in the figure) to vary the Master Clock frequency: (1) The Stretch latch allows for micro- programmed switching of the Master Clock to one-half its frequency. This latch is activated by the control line "Stretch This T-state" which is microcoded for those T-states of an instruction which are to be doubled from 40 nanoseconds to 80 nanoseconds. (2) By the execution of a "Wait on Event" Instruction by the CPU. This special type of user codable instruction causes the WOE latch to set, stopping the clock entirely until the line "User Restart from Woe" is activated by user-attached hardware. (3) The occurrence of an external stop condition. For example, the stop line is activated after the execution of every instruction when in single instruction execution mode. (4) The insertion of 10-nanosecond wait states for asynchronous external register communication. (...