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Microprocessor High Speed ALU Output Buffer Using Parallel Logic to Increase Throughput and Function While at the Same Time Adhering to an I/O Constraint

IP.com Disclosure Number: IPCOM000042962D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Fleurbaaij, JM: AUTHOR [+2]

Abstract

Fig. 1 shows the arithmetic logic unit (ALU) portion of a typical microprocessor's central processing unit (CPU). This CPU improves on the data manipulation capabilities of a simple combinatorial ALU by utilizing a higher function ALU output buffer (elements 1 and 2). These functions include bit shifting of data right or left and byte swapping of data prior to sending the data to the System Data Out Bus. With this increased function comes a penalty in delay time for those instructions needing non-manipulated or straight ALU Out data. In past designs, this delay was reduced by providing a separate data bus, fed directly by the ALU output, to those system elements requiring only straight ALU Out data.

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Microprocessor High Speed ALU Output Buffer Using Parallel Logic to Increase Throughput and Function While at the Same Time Adhering to an I/O Constraint

Fig. 1 shows the arithmetic logic unit (ALU) portion of a typical microprocessor's central processing unit (CPU). This CPU improves on the data manipulation capabilities of a simple combinatorial ALU by utilizing a higher function ALU output buffer (elements 1 and 2). These functions include bit shifting of data right or left and byte swapping of data prior to sending the data to the System Data Out Bus. With this increased function comes a penalty in delay time for those instructions needing non-manipulated or straight ALU Out data. In past designs, this delay was reduced by providing a separate data bus, fed directly by the ALU output, to those system elements requiring only straight ALU Out data. With the present emphasis on higher integration of logic to fewer and fewer cards, the number of input/output (I/O) pins available to support additional data busses become fewer and fewer as well. This design supports a single System Data Out Bus, yet significantly reduces the data delay by the use of transparent latches (element 3) with tri-state outputs. The Bus Data Source Selection Control Logic accomplishes this by putting the byte multiplexer outputs of ALOB I into the high-impedance state and enabling the transparent latches output (ALOB II) for those instructions not needing shifted or swapped data. This para...