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Imbedded System Clocking for Logic Circuits

IP.com Disclosure Number: IPCOM000042967D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Cole, TA: AUTHOR [+4]

Abstract

An imbedded system clocking technique for differential clocked logic circuits is provided by utilizing level sensitive scan design (LSSD) latch locks as the combinatorial logic circuit clocks. The technique imbeds the typical two-phase, along with sub-phases, system clocks into the design of a logic family. To achieve testability, logic chip designs conform to known LSSD rules which, in general, specify that combinatorial logic inputs and outputs be encompassed by set reset latch (SRL) master/slave latches connected into scan loops. The following rules have been devised as sufficient to imbed the LSSD SRL system clocks in differential clocked logic: 1. Precharge the entire logic group by the complement of the latest clock in time which sets those input latches to that particular group. 2.

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Imbedded System Clocking for Logic Circuits

An imbedded system clocking technique for differential clocked logic circuits is provided by utilizing level sensitive scan design (LSSD) latch locks as the combinatorial logic circuit clocks. The technique imbeds the typical two-phase, along with sub-phases, system clocks into the design of a logic family. To achieve testability, logic chip designs conform to known LSSD rules which, in general, specify that combinatorial logic inputs and outputs be encompassed by set reset latch (SRL) master/slave latches connected into scan loops. The following rules have been devised as sufficient to imbed the LSSD SRL system clocks in differential clocked logic: 1. Precharge the entire logic group by the complement of the latest clock in time which sets those input latches to that particular group. 2. Precharge parts of the logic group by the complement of the latest clock in time which sets the input latches to those parts of the logic group.
3. Precharge the logic group by the clock complement which sets input latches, not necessarily the latest, such that performance degradation occurs due to skew. This implies a non-clocked-type logic tree. In rule 2, sufficient time must be allowed such that the input signals to the latest precharge circuits have settled; otherwise, isolation and preconditioning circuitry is needed. This method can be used to speed up the logic group through staggering late and early arriving input signals. Rule 3 implies regenerative circuitry is present within each logic tree. A requirement of the logic family is for all inputs to be valid or start low, then go high a...