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Logic Optimization of a 4-Bit Up/Down Counter

IP.com Disclosure Number: IPCOM000042969D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Blachere, JM: AUTHOR [+2]

Abstract

An up/down counter is described using an OR-AND-OR invert circuit (OAOI) to generate the input to the next bit. The figure shows 2 bits of this counter design with LSSD polarity-hold latches. Input/output signals used are: C/B : master/slave clocks DN : data input of bit N DU : incrementing or decrementing control input DU = 1: down counting; DU = 0: up counting. CI : carry input used to serialize several counters L2N,L2N : slave outputs of bit N At the data input of the polarity-hold latch N, the logic function required for the implementation of the up/down counter is shown below: (Image Omitted) Usually, this function is generated by using 2 XORs and 1 OI circuits for each bit of the counter.

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Logic Optimization of a 4-Bit Up/Down Counter

An up/down counter is described using an OR-AND-OR invert circuit (OAOI) to generate the input to the next bit. The figure shows 2 bits of this counter design with LSSD polarity-hold latches. Input/output signals used are: C/B : master/slave clocks DN : data input of bit N DU : incrementing or decrementing control input DU = 1: down counting; DU = 0: up counting. CI : carry input used to serialize several counters L2N,L2N : slave outputs of bit N At the data input of the polarity-hold latch N, the logic function required for the implementation of the up/down counter is shown below:

(Image Omitted)

Usually, this function is generated by using 2 XORs and 1 OI circuits for each bit of the counter. After the slave outputs (L2, L2) are valid, this implementation requires 5 elementary circuit delays to generate the data input (1 XOR is equivalent to 2 circuits). This article describes this function generated with only 1 XOR and 1 OAOI circuits. After the slave outputs are valid, this implementation requires only 3 circuit delays to generate the data input and allows an increase in the operation frequency of the counter. In addition, by saving 1 XOR/bit, the macro area and the power dissipation of the counter are decreased. For a 4-bit up/down counter designed using the structured approach in NMOS technology, savings have been evaluated to 15% for the power dissipation and 16% for the macro area.

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