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High Speed Cascode Emitter Coupled Logic and Circuit

IP.com Disclosure Number: IPCOM000042980D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Blum, DW: AUTHOR

Abstract

By limiting the voltage rise of internal floating nodes, the power performance of a cascode emitter coupled logic circuit is improved. A four-input cascode emitter coupled logic AND circuit is shown in the figure which has inputs A,A, B,B, C,C and D,D with output terminals at Q and Q . When D is high, all current flowing through the current source including transistor TCS and resistor RCS is directed through transistor T2, except for a small amount of leakage current which flows through transistors T1, T3, T5 and T7. As a result of reduced T3, T5 and T7 base-emitter voltage required to support this low level of leakage current, over a period of time the voltage on nodes 1, 2 and 3 tends to increase to a level between 0.2 and 0.3 volt below the up level base of the next higher transistor pair; i.e.

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High Speed Cascode Emitter Coupled Logic and Circuit

By limiting the voltage rise of internal floating nodes, the power performance of a cascode emitter coupled logic circuit is improved. A four-input cascode emitter coupled logic AND circuit is shown in the figure which has inputs A,A, B,B, C,C and D,D with output terminals at Q and Q . When D is high, all current flowing through the current source including transistor TCS and resistor RCS is directed through transistor T2, except for a small amount of leakage current which flows through transistors T1, T3, T5 and T7. As a result of reduced T3, T5 and T7 base-emitter voltage required to support this low level of leakage current, over a period of time the voltage on nodes 1, 2 and 3 tends to increase to a level between 0.2 and 0.3 volt below the up level base of the next higher transistor pair; i.e., the voltage at node 1 would rise to a voltage which is 0.2 to 0.3 volt below the voltage level at the base of transistors T3 and T4. In this condition, when the D,D input is switched so that transistor T1 turns on, nodes 1, 2 and 3 must be consecutively discharged 0.5 to 0.6 volt before transistors T3, T5 and T7 can turn on to pull down output Q. The delay t, the time between the turn-off of transistor T2 and the time when output Q begins to pull down, which is attributed primarily to the discharge delays at nodes 1, 2 and 3, may be approximately 5 nanoseconds. To eliminate, or at least minimize, the delay t, means are provided for increasing the current flow out of the floating nodes 1, 2 and 3 to a level which is several orders of magnitude higher than the leakage current flowing into nodes 1, 2 and 3. This ad...