Browse Prior Art Database

Display Architecture to Allow Rapid Updating of a Bit-Mapped Display With Automatic Regeneration of Affected Elements

IP.com Disclosure Number: IPCOM000042985D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 30K

Publishing Venue

IBM

Related People

Evangelisti, CJ: AUTHOR [+2]

Abstract

In a raster display system the erasure of one image which is superimposed on another image will inadvertently erase any points held in common by the two images. This invention describes the means of driving a raster display from a display list, avoiding both this problem of erasure and the time delay in introducing new elements to the display list. The most important aspect of this technique is that modifications to the display are rapidly generated so that immediate feedback may be given to the user. The integrity of the display is subsequently preserved with a "healing" process. Raster displays normally use a bit buffer for regeneration of the image displayed. The techniques for translating display elements, such as vectors and characters, to a bit buffer are well known and are not discussed here.

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Display Architecture to Allow Rapid Updating of a Bit-Mapped Display With Automatic Regeneration of Affected Elements

In a raster display system the erasure of one image which is superimposed on another image will inadvertently erase any points held in common by the two images. This invention describes the means of driving a raster display from a display list, avoiding both this problem of erasure and the time delay in introducing new elements to the display list. The most important aspect of this technique is that modifications to the display are rapidly generated so that immediate feedback may be given to the user. The integrity of the display is subsequently preserved with a "healing" process. Raster displays normally use a bit buffer for regeneration of the image displayed. The techniques for translating display elements, such as vectors and characters, to a bit buffer are well known and are not discussed here. This architecture proposes the use of two processors (A and B), both of which access the bit buffer. Processor A will scan the display list of coded information in the usual manner, generating the image for each display element in the bit buffer. It will cycle through the display list sequentially and continuously, returning to the top element of the list when it has completed generating the last element. It normally takes the processor many times longer to scan through the display list than it does to display the total image on the screen (one frame). In the simplest version, processor A would scan through the entire display list to build one raster line of display in the bit buffer. Processor A can only add ("logical OR") to the bit buffer. Processor B can add ("logical OR") to the bit buffer or delete ("logical AND") from the bit buffer. It executes the display commands only once as they are added to or deleted from the image, and it has a first-in, first-out (FIFO) queue for the display commands. Processor B will typically complete execution of the display commands in the queue in less than one display (frame) time, but this is not a requiremen...