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Design for Testability of an Adder With Duplicate Carry Generation Logic

IP.com Disclosure Number: IPCOM000042987D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Hanna, SD: AUTHOR

Abstract

This article describes the design of an adder including a standard duplicate carry network with logic for comparing the duplicate carries in order to detect errors in the carries. To check for faults in the comparison logic, a shifter is interposed between one of the adder input operands and the duplicate carry network. In test mode, particular operand values are entered and the shifted operand forces an error (or errors), thereby testing the comparison logic and the added shifter logic. This adder design allows the forcing of "errors" in the inputs to the logic which compare the duplicate carry generation outputs.

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Design for Testability of an Adder With Duplicate Carry Generation Logic

This article describes the design of an adder including a standard duplicate carry network with logic for comparing the duplicate carries in order to detect errors in the carries. To check for faults in the comparison logic, a shifter is interposed between one of the adder input operands and the duplicate carry network. In test mode, particular operand values are entered and the shifted operand forces an error (or errors), thereby testing the comparison logic and the added shifter logic. This adder design allows the forcing of "errors" in the inputs to the logic which compare the duplicate carry generation outputs. Carry logic is duplicated because an adder which has parity prediction (based on the parity of the two inputs and the parity of the carry) can have pairs of errors in the sum if the carry logic is not working properly. As a consequence, the errors are not detectable as a parity error. Note that the two carries are generated differently. The primary carry (the one used to generate the sum) is a carry lookahead carry. The second carry is generated from the first carry (not the same bit but an earlier bit). An example of the adder in its four carry generation modes is shown below. The adder has two input buses, a 23-bit bus (called 'A') and a 5-bit bus (called 'B'). The output sum is called 'S', the carry lookahead carry is called 'C', and the duplicate (semi-ripple) carry is called 'CC'. The compare of the carries is called CCHK. (='1' is an error.) This method of error forcing, i.e., shifting of carry bits into the carry compare logic, was chosen because the adder has different length input terms and therefore cannot achieve all combinations of carry bits. This method, however, will work on an adder with equal length input terms as well. For example, if the carry for bit 15 is a '1...