Browse Prior Art Database

Pre-Emptive Switching Within a Multiprocessor

IP.com Disclosure Number: IPCOM000042988D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Foss, ED: AUTHOR [+4]

Abstract

In a multi-processor in which any one processor may have a control of a facility, such as a loop, at a time, each processor is provided with a pre-emptive switching facility to force control reconnection of the facility to itself and away from the current controlling processor, without manual intervention, in addition to the conventional control switching arrangements by which a processor can relinquish control of the facility. In this way, a processor, which has control and becomes faulty, cannot lock the system in a wholly or partially inoperative condition, requiring the attention of an engineer to free the lock. As shown in the figures, and for simplicity of description, the pre-emptively switched facility is a peripheral loop, having two lobes L1, L2 and controlled by either of two processors A, B.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Pre-Emptive Switching Within a Multiprocessor

In a multi-processor in which any one processor may have a control of a facility, such as a loop, at a time, each processor is provided with a pre-emptive switching facility to force control reconnection of the facility to itself and away from the current controlling processor, without manual intervention, in addition to the conventional control switching arrangements by which a processor can relinquish control of the facility. In this way, a processor, which has control and becomes faulty, cannot lock the system in a wholly or partially inoperative condition, requiring the attention of an engineer to free the lock. As shown in the figures, and for simplicity of description, the pre-emptively switched facility is a peripheral loop, having two lobes L1, L2 and controlled by either of two processors A, B. The switching mechanism is shown as a combination of relays, though the pre-emptive switching can be performed by other hardware arrangements. Referring to Fig. 1, each processor A, B supports a plurality of communication adapters, two communication adapters 1, 2 being shown for each processor, each of which can service loop adapters 3, 4, 5. The loop adapters 3, 4 of one communication adapter 1 of each processor provide the loop connections, while the loop adapter 5 of the other communications adapter 2 of each processor provides the pre-emptive control over those connections. All the loop adapters connect to one or the other of two switch units SL1, SL2, one for each lobe, which connect to the appropriate lobe through a physical connector 6. The actual switching is performed in the switch units and is illustrated for one lobe in Fig. 2, in which many of the units shown in Fig. 1 have been omitted. The lobe L1 has a transmit connection 7 (Fig. 2) and a receive connection 8 to each processor through a corresponding loop adapter 3, and each transmit connection includes a relay-controlled contact. Basic disconnection is effected by breaking the transmit contacts. The transmit relays are driven by one loop adapter of each processor. The circuit of the transmit relay 11 of each processor includes the contact 12 of a pre-emptive relay 13 driven by the loop adapter 5 of the other processor. The transmit contacts complete the lobe and disconnect from the transmit connection when the relay is inactive and create a discontinuity in the lobe and connect to the transmit connection when the transmit relay is active. The pre-emptive relay renders its transmit relay inactive. The pre-emptive relays are cross-coupled by inc...