Browse Prior Art Database

Intelligent Instruction Buffer

IP.com Disclosure Number: IPCOM000042997D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

For a cache with a wider readout than the bus to other functional units, the access can cause a buffer(s) to be loaded. In the case of an I-fetch access, such buffer(s) are likely to contain not only subsequent instructions required by the processor but also the targets of short forward/backward-taken branches. Since module crossings are time consuming, the buffering and logic associated with the Intelligent Instruction Buffer (IIB) (figure) will be maintained on the cache module. To prefetch the target of a taken branch, the IIB must: (A) Detect the branch - since the IIB passes instructions to the I-unit, a simple comparison of the OP code - X '47' detects the BC instruction. (B) Determine if it is taken - a decode history table can use the address of the detected BC to determine if it is taken (guess).

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Intelligent Instruction Buffer

For a cache with a wider readout than the bus to other functional units, the access can cause a buffer(s) to be loaded. In the case of an I-fetch access, such buffer(s) are likely to contain not only subsequent instructions required by the processor but also the targets of short forward/backward-taken branches. Since module crossings are time consuming, the buffering and logic associated with the Intelligent Instruction Buffer (IIB) (figure) will be maintained on the cache module. To prefetch the target of a taken branch, the IIB must: (A) Detect the branch - since the IIB passes instructions to the I-unit, a simple comparison of the OP code - X '47' detects the BC instruction. (B) Determine if it is taken - a decode history table can use the address of the detected BC to determine if it is taken (guess). (C) Find the target within the buffer (if it is there) - the finding of the target of the BC uses only the D-field (displacement) of the BC instruction. The displacement D of the BC instruction is compared to the putative D0, D1, ..., Dn of the N-buffers via a simple subtraction operation. This establishes the buffer in which the target is found (high-order field) and the location within the buffer (low- order field). The width of the adder and comparators relate to the size of the readout (buffer). For a 64-byte buffer, a single 6-bit adder and (N+1) - 6-bit comparators will suffice to handle the N-buffer (64B). The process is ini...