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Design of Highly Reliable Memory for Small Systems (Personal Computer and Display Products)

IP.com Disclosure Number: IPCOM000043009D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Raheja, RK: AUTHOR [+2]

Abstract

Due to the proportionately higher cost of implementing error correcting code, very small capacity memories of less than 1 Mbyte organized in 8-bit or 16-bit wide memory words seldom take advantage of error correcting codes. For example, an 8-bit wide memory utilizing a single error correction/double error detection (SEC/DED) code requires an additional five check bits. This translates into approximately a 43% bit overhead as compared to when only byte parity for simple error detection is used. The logic overhead for implementing the code can also be proportionately high for memory sub-systems in the small memory sub-system application area, where comparative cost pressures are substantial. Therefore, memory sub-system reliability/availability due to cost reasons alone is less than desired.

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Design of Highly Reliable Memory for Small Systems (Personal Computer and Display Products)

Due to the proportionately higher cost of implementing error correcting code, very small capacity memories of less than 1 Mbyte organized in 8-bit or 16-bit wide memory words seldom take advantage of error correcting codes. For example, an 8-bit wide memory utilizing a single error correction/double error detection (SEC/DED) code requires an additional five check bits. This translates into approximately a 43% bit overhead as compared to when only byte parity for simple error detection is used. The logic overhead for implementing the code can also be proportionately high for memory sub-systems in the small memory sub- system application area, where comparative cost pressures are substantial. Therefore, memory sub-system reliability/availability due to cost reasons alone is less than desired. A memory sub-system design method is described herein by which memory reliability/availability can be improved by two or three orders of magnitude at a very nominal cost increase over byte-wide parity designs. The method is based on using two techniques in sub-system design which can be used in complementary fashion. These techniques are (a) double complementing technique for restructuring the error data words and (b) the use of a one spare chip/card design. The double complementing technique is used for recovering correct data in error situations arising from random array cell hard-fails. As shown in Fig. 1, the technique works after the memory word is found to contain a bit error. The read word is complemented and written back in the same address location from which it was read. The word is again read and complemented. If the parity check shows no error, then the error due to hard fail has been corrected and can be used by the system. If the parity check still shows an error, then it is concluded that the error is non-reproducible and the processor is stopped. The system is as...