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Carry-Propagate Address Incrementer With Self-Timed Interlocking Enable Circuits

IP.com Disclosure Number: IPCOM000043018D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 4 page(s) / 71K

Publishing Venue

IBM

Related People

Matick, RE: AUTHOR

Abstract

This invention provides a unique and practical way of implementing a useful logic function onto a random-access (RAM) chip, which is very desirable for bit buffered displays and other applications. Certain types of functional memory require an address-incrementing function to be included on the memory chip. This function is merely the addition of 1 to the given address whenever the separate "increment" pin is valid, and an addition of 0 when the increment pin is not valid. Although this incrementing function can be obtained in various ways on a memory chip, the most straightforward and economical method is to use a 1-bit carry propagate "adder" on the desired address pins, prior to presenting the signals to the decoder. In principle, the inclusion of a 1-bit adder should be a trivial logic function to any logic circuit.

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Carry-Propagate Address Incrementer With Self-Timed Interlocking Enable Circuits

This invention provides a unique and practical way of implementing a useful logic function onto a random-access (RAM) chip, which is very desirable for bit buffered displays and other applications. Certain types of functional memory require an address-incrementing function to be included on the memory chip. This function is merely the addition of 1 to the given address whenever the separate "increment" pin is valid, and an addition of 0 when the increment pin is not valid. Although this incrementing function can be obtained in various ways on a memory chip, the most straightforward and economical method is to use a 1-bit carry propagate "adder" on the desired address pins, prior to presenting the signals to the decoder. In principle, the inclusion of a 1-bit adder should be a trivial logic function to any logic circuit. However, memory chips, in general, have special requirements which place additional demands on the peripheral circuits. First, such circuits are often dynamic or quasi-static and they do not usually have only two stable states 1 and 0. They are often designed to have three usable states, 1,0, and precharged state (true and complement at same voltage level) which is "locally" undefined. The nature of these circuits is such that they are precharged during the quiescent or unselected state. When selected, charge must be drained off appropriate nodes, but not off others. In a pure dynamic circuit, if charge is inadvertently drained off the wrong nodes due to timing problems, the charge cannot be restored until the next cycle giving false data for the current cycle, i.e., the circuits latch or, another way of looking at it, they have an infinite number of stable states. Quasi-static circuits also use a precharge state but do not necessarily latch at intermediate states due to partial discharge of incorrect nodes. However, glitches (large voltage swing in the wrong direction which is then reversed when a correct logic signal arrives) can become serious, producing additional noise and possibly timing constraints. Therefore, an address incrementer which is to be suitable for implementation in both dynamic and quasi-static circuits must be designed to allow precharging, as well as avoiding false discharging into an undefined state. Another difficulty with interfacing logic circuits to memory chips is that the timing between certain gross events is crucial for proper access to data. For instance, on some RAM chips, it is necessary that the bit address lines be all valid before the word decoding is started. This interlock is achieved by using the two slowest bit (y) address lines as an Enable function on the word line decoder. A CLAMP circuit holds all word decoders off until the worst-case y lines are valid. As a result, the simplest way to insert a bit- address-incrementer while avoiding extensive physical design or redoing circuit design is to...