Browse Prior Art Database

Multiplexed Sense Amplifier With Temporary Storage

IP.com Disclosure Number: IPCOM000043022D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR [+3]

Abstract

Noise coupling associated with crosstalk in a multiplexed sense amplifier is eliminated or at least substantially reduced by temporarily storing data in intermediate capacitors located between the sense amplifier and bit/sense lines of, e.g., a memory of the type described in U.S. Patent 4,080,590. As shown in the figure, bit/sense lines BSL1, BSL2, BSR1 and BSR2 are connected to nodes NA and NB of sense amplifier 10 through transistors T1 and T2, T3 and T4, T5 and T6, and T7 and T8, respectively. Intermediate capacitors CI1, CI2, CI3 and CI4 are connected to the common point between transistors T1 and T2, T3 and T4, T5 and T6, and T7 and T8, respectively.

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Multiplexed Sense Amplifier With Temporary Storage

Noise coupling associated with crosstalk in a multiplexed sense amplifier is eliminated or at least substantially reduced by temporarily storing data in intermediate capacitors located between the sense amplifier and bit/sense lines of, e.g., a memory of the type described in U.S. Patent 4,080,590. As shown in the figure, bit/sense lines BSL1, BSL2, BSR1 and BSR2 are connected to nodes NA and NB of sense amplifier 10 through transistors T1 and T2, T3 and T4, T5 and T6, and T7 and T8, respectively. Intermediate capacitors CI1, CI2, CI3 and CI4 are connected to the common point between transistors T1 and T2, T3 and T4, T5 and T6, and T7 and T8, respectively. In the operation of the circuit shown in the figure for reading information stored in cells 1 and 2, pulses are applied to terminals LDA and LDB to turn on the transistors T1, T3, T6 and T8. Word line WL1 and dummy word line WLD are turned on to develop data signals on bit/sense lines BSR1 and BSR2 and dummy signals on bit/sense lines BSL1 and BSL2, respectively, which turn on transistors T1, T3, T6 and T8. Bit/sense lines BSL1, BSL2, BSR1 and BSR2 are recharged to the cut-off point of transistors T1, T3, T6 and T8 by charge from intermediate capacitors CI1, CI2, CI3, and CI4. The voltage on terminals LDA and LDB is now pulsed to a low value, such as ground, storing dummy and data signals in intermediate capacitors CI1 and CI2, and CI3 and CI4, respectively. The dummy and data signals stored in intermediate capaci...