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Random-Access Memory Based Direct Memory Access

IP.com Disclosure Number: IPCOM000043036D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Shaughnessy, JP: AUTHOR

Abstract

A mixture of random-access memory (RAM) and bipolar large-scale integrated circuitry is utilized to achieve a cost effective direct-memory access (DMA) controller in a system requiring many DMA channels. This technique allows an increase in the number of channels and the address range in an economical and efficient manner. To implement the RAM-based DMA controller, the data flow structure must allow initialization of the DMA RAM by a processor. When the DMA cycle is granted, it must fetch the current DMA channel address, control, and block count from the RAM. At the beginning of the DMA cycle the controller must gate out addresses and read/write controls. During the DMA cycle it must increment both the address count and block count, and store them back in the DMA RAM.

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Random-Access Memory Based Direct Memory Access

A mixture of random-access memory (RAM) and bipolar large-scale integrated circuitry is utilized to achieve a cost effective direct-memory access (DMA) controller in a system requiring many DMA channels. This technique allows an increase in the number of channels and the address range in an economical and efficient manner. To implement the RAM-based DMA controller, the data flow structure must allow initialization of the DMA RAM by a processor. When the DMA cycle is granted, it must fetch the current DMA channel address, control, and block count from the RAM. At the beginning of the DMA cycle the controller must gate out addresses and read/write controls. During the DMA cycle it must increment both the address count and block count, and store them back in the DMA RAM. To address the DMA RAM, a bus arbiter function, which normally indicates which DMA channel is selected, also points to the block of RAM that contains the next address, count, and control for the channel. The data flow controller drives some of the low address bits depending on how many fetches are required. In clock cycle 1 (Fig. 2), upon receiving a "bus grant" from the arbiter a data flow controller fetches word zero of the channel block selected by the arbiter. Word zero is latched in register 0 of the data flow and the address portion (SA16-19, B/W) is also latched in one of the system address bus latches, as shown in Fig. 1. In clock cycle 2, word...