Browse Prior Art Database

Timing Chain With Laser-Programmable Delay

IP.com Disclosure Number: IPCOM000043038D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Ellenberger, A: AUTHOR [+3]

Abstract

In this on-chip timing chain for controlling the drivers of a memory or like apparatus, the driver-to-driver delay provided by the chain can be adjusted by means of laser-fusible links positioned in the path from a clock input terminal to the respective gates of several charge transfer devices whose channels are parallel-connected. When the desired timing chain delay differs from the delay that would be provided if all of the fusible gate links were left intact, a laser beam then is directed at a chosen one or ones of these links to interrupt them selectively according to the amount of delay required. When characterizing hardware that functions from an on-chip timing chain, much data can be obtained on process and circuit limited yields by being able to adjust delays in the timing chain.

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Timing Chain With Laser-Programmable Delay

In this on-chip timing chain for controlling the drivers of a memory or like apparatus, the driver-to-driver delay provided by the chain can be adjusted by means of laser-fusible links positioned in the path from a clock input terminal to the respective gates of several charge transfer devices whose channels are parallel-connected. When the desired timing chain delay differs from the delay that would be provided if all of the fusible gate links were left intact, a laser beam then is directed at a chosen one or ones of these links to interrupt them selectively according to the amount of delay required. When characterizing hardware that functions from an on-chip timing chain, much data can be obtained on process and circuit limited yields by being able to adjust delays in the timing chain. This cannot readily be accomplished with conventional timing chains such as the one shown in Fig. 1, which controls the drivers of a RAM or ROM. In this circuitry the FET devices 4 and 5 determine the driver-to-driver delay by the rate at which they discharge the node D. The usual methods of controlling the delay in this type of chain utilize techniques such as adding capacitance internally by means of probes or externally by other means, or overriding the driver with a pulse generator, none of which have proved satisfactory in practice. Fig. 2 shows a timing chain driver which provides a more effective way of controlling delay. In this...