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Methods for Optimizing a Memory Interface by Utilizing Microprocessor Instruction and Exception Flows

IP.com Disclosure Number: IPCOM000043047D
Publication Date: 2005-Feb-04
Document File: 8 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Related People

Keith E. Kinerk: AUTHOR [+3]

Abstract

Microprocessor performance (measured in Cycles-per-instruction, or CPI) is limited by the access time (number of cycles per memory access) of memory containing the software being executed. This paper describes various related methods to reduce the access times of memory in a microprocessor-based system resulting in increased performance. Recognizing that a microprocessor is capable of a fixed set of pre-defined operations allows for optimization of performance by reducing the effective access time of memory. This paper describes the design of a memory interface controller that would reduce the memory access times for the microprocessor for five categories of microprocessor operations. The categories discussed are: Change of flow operations (Jump, Branch, Conditional Branch, etc…), Data accesses (Load, Store, etc…), Program Counter based operations (Relative addressing modes, etc…), Multi-cycle instructions, and Exceptions. The paper describes the design of a memory interface controller that can predict future microprocessor memory accesses based on the category of operation that is being requested or executed by the microprocessor at any given time. Additional benefits beyond microprocessor performance that are discussed in the paper include power reduction and improved scheduling for multi-master, cache-based, and SDRAM based systems.

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Methods for Optimizing a Memory Interface by

Utilizing Microprocessor Instruction and Exception

Flows

Authors:

Keith E. Kinerk

Brett Murdock

Craig Shaw

 


Abstract:

       Microprocessor performance (measured in Cycles-per-instruction, or CPI) is limited by the access time (number of cycles per memory access) of memory containing the software being executed. This paper describes various related methods to reduce the access times of memory in a microprocessor-based system resulting in increased performance. Recognizing that a microprocessor is capable of a fixed set of pre-defined operations allows for optimization of performance by reducing the effective access time of memory.  This paper describes the design of a memory interface controller that would reduce the memory access times for the microprocessor for five categories of microprocessor operations.  The categories discussed are: Change of flow operations (Jump, Branch, Conditional Branch, etc…), Data accesses (Load, Store, etc…), Program Counter based operations (Relative addressing modes, etc…), Multi-cycle instructions, and Exceptions.  The paper describes the design of a memory interface controller that can predict future microprocessor memory accesses based on the category of operation that is being requested or executed by the microprocessor at any given time.   Additional benefits beyond microprocessor performance that are discussed in the paper include power reduction and improved scheduling for multi-master, cache-based, and SDRAM based systems. 

     A microprocessor is a machine defined by a finite set of instruction operations. Each instruction operation is well defined and affects the memory subsystem in a predictable manner based on the state of the machine. Operations that result in an access to memory typically require more time to execute than operations that do not access memory. In a typical system, the memory controller is a slave of the microprocessor and issues memory accesses only when requested by the microprocessor. This results in several inefficiencies when accessing memory and reduces the overall performance of the microprocessor.

This paper describes the design of an external memory controller that is capable of anticipating future operations of the microprocessor. The memory controller does this by interpreting instructions as they are fetched from memory and uses knowledge of the processor operation to issue future memory accesses before they are requested by the microprocessor. Operations in which this invention will improve performance are described below:

1.      Jump Instructions and Unconditional Branches

  • Jump instructions and unconditional branches are instructions that force a change in location for program operation. The memory controller is designed to decode these types of instructions and generate the memory access to the target of the Jump/branch before the microprocessor issues the request. In a system with an L1 Cache, it is poss...