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Utilization of Pre-Silicide Spacer for Ultra-Shallow Junction Devices

IP.com Disclosure Number: IPCOM000043051D
Publication Date: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database

Related People

Sinan Goktepeli: AUTHOR [+2]

Abstract

Scaling of devices for 90 and 65 nm device nodes require junctions more abrupt and shallower than what can be achieved with conventional anneals. Experiments performed with low peak-temperature spike anneals have shown degradation in transistor on current with decreasing peak spike temperatures. The process and device simulations have given a similar trend. Analysis of the simulation results and verification with experimental data, the nMOS degradation is tied to a constricted current path between salicide and junction where SDE and SD join. The dopant concentration in this region decreases with decreasing peak temperature, increasing the SD-SDE resistance. Simulations showed that utilization of pre-salicide spacer can effectively eliminate the necking issue. This allows low thermal budget nMOS transistors to exceed the performance of higher thermal budget transistors, resulting in a projected overall improvement in ring oscillator speed.

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Utilization of Pre-Silicide Spacer for Ultra-Shallow Junction Devices

Sinan Goktepeli and Jian Chen

Abstract

Scaling of devices for 90 and 65 nm device nodes require junctions more abrupt and shallower than what can be achieved with conventional anneals. Experiments performed with low peak-temperature spike anneals have shown degradation in transistor on current with decreasing peak spike temperatures. The process and device simulations have given a similar trend. Analysis of the simulation results and verification with experimental data, the nMOS degradation is tied to a constricted current path between salicide and junction where SDE and SD join. The dopant concentration in this region decreases with decreasing peak temperature, increasing the SD-SDE resistance. Simulations showed that utilization of pre-salicide spacer can effectively eliminate the necking issue. This allows low thermal budget nMOS transistors to exceed the performance of higher thermal budget transistors, resulting in a projected overall improvement in ring oscillator speed.

The scaling of devices beyond 0.1um requires ultra-shallow junctions (USJ) without comprising activation or increasing the sheet resistance. The implantation dose is being increased to control series resistance, while the implantation energy is being decreased.

The implanted dopants require a thermal step to be activated. The high amount of defects generated during source/drain extension (SDE) and source/drain (SD) ion implantations cause transient enhanced diffusion (TED) during the activation anneal. For the conventional rapid thermal anneal (RTA), the TED takes place during the ramp-up. Further diffusion with the equilibrium point defects result in graded, deeper junctions. The high concentration of the dopants result in clustering during the RTA, resulting in loss of active concentration.

Reduction of anneal times through increased ramp up and ramp down rates, and achievement of abru...