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Select 1 of N Multiplexer

IP.com Disclosure Number: IPCOM000043054D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+3]

Abstract

A 1 of N multiplexer in complementary metal oxide semiconductor (CMOS) technology provides higher speeds and improved density over known static multiplexers. More particularly, this select 1 of N multiplexer is provided in a differential cascode voltage switch arrangement with true and complement outputs. In Fig. 1, a multiplexer for selecting 1 of 2 input signals D0 or D1, and their complements D0 and D1, respectively, includes field-effect transistors P1 and P2, each having a P channel, and field-effect transistors N1, N2, N3, N4, N5 and N6, each having an N channel. In the operation of this multiplexer, it can be seen that when selector pulse S0 is high, selector pulse S0 is low and, therefore, input D1 is selected with the output signal being produced in inverted form at terminal Q and in true form at terminal Q.

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Select 1 of N Multiplexer

A 1 of N multiplexer in complementary metal oxide semiconductor (CMOS) technology provides higher speeds and improved density over known static multiplexers. More particularly, this select 1 of N multiplexer is provided in a differential cascode voltage switch arrangement with true and complement outputs. In Fig. 1, a multiplexer for selecting 1 of 2 input signals D0 or D1, and their complements D0 and D1, respectively, includes field-effect transistors P1 and P2, each having a P channel, and field-effect transistors N1, N2, N3, N4, N5 and N6, each having an N channel. In the operation of this multiplexer, it can be seen that when selector pulse S0 is high, selector pulse S0 is low and, therefore, input D1 is selected with the output signal being produced in inverted form at terminal Q and in true form at terminal Q. When selector pulse S0 is low, S0 is high and, therefore, input D0 is selected with again the output signal being produced in inverted form at terminal Q and in true form at terminal Q. Fig. 2 is similar to the circuit of Fig. 1, being formed as two of the circuits of Fig. 1 connected in parallel with additional selector transistors N7 and N8, to provide a 1 of 4 multiplexer. The duplicate elements are identified as N channel transistors N1' to N6'. The four input signals are D0, D1, D2 and D3 with their complements D0, D1, D2 and D3, respectively. It can be seen that if selector pulse S1 is high, either input signal D0 or D...