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Emitter-Coupled Multi-Port RAM Implemented in Cascode Logic

IP.com Disclosure Number: IPCOM000043055D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 4 page(s) / 69K

Publishing Venue

IBM

Related People

Kovach, PS: AUTHOR [+2]

Abstract

Emitter-coupled random-access memory (RAM) arrays are implemented in cascode logic technology. The arrays are operable as a multi-port array (with simultaneous read and write operations at the same or different address locations), and are also operable as a conventional RAM array (with mutually exclusive read and write operations for each port) by an appropriate slight modification to the addressing scheme. Specific two and three port RAM array configurations and their array cell circuits configured in cascode current switch (CSS) networks are described. Partially shown dual-port RAM array 1 (Fig. 1) is part of a rectangular matrix of identical storage cells 2. It has a certain storage capacity, e.g., 32 words of 32 bits each.

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Emitter-Coupled Multi-Port RAM Implemented in Cascode Logic

Emitter-coupled random-access memory (RAM) arrays are implemented in cascode logic technology. The arrays are operable as a multi-port array (with simultaneous read and write operations at the same or different address locations), and are also operable as a conventional RAM array (with mutually exclusive read and write operations for each port) by an appropriate slight modification to the addressing scheme. Specific two and three port RAM array configurations and their array cell circuits configured in cascode current switch (CSS) networks are described. Partially shown dual-port RAM array 1 (Fig. 1) is part of a rectangular matrix of identical storage cells 2. It has a certain storage capacity, e.g., 32 words of 32 bits each. Each cell 2 has a READ signal input R, a WRITE CLOCK signal input W, DATA IN signal input DI and a DATA OUT signal output DO. The DATA IN, WRITE CLOCK and DATA OUT signals also have complementary counterpart signals (not shown) for which each cell 2 also has corresponding complementary inputs DI', W' and DO', respectively, (Fig. 2). As is customary, each of the inputs W, W' and R of a cell 2 is commonly connected to their like inputs W, W' and R of the other cells 2 of the same row
(i.e., same memory word); whereas, each of the inputs DI, DI' and each of the outputs DO, DO' of a cell 2 is commonly connected to their like inputs DI, DI' and outputs DO, DO' of the other cells 2 of the same column (i.e., the same corresponding bit locations in the different memory words). Each of the row lines
(i.e., the 32 READ lines 1R, 2R, etc., the 32 WRITE CLOCK lines 1W, 2W, etc., and the latter's 32 NOT counterpart lines, (not shown)) require a separate driver (not shown). For dual-port applications, two separate address decoders (not shown) address the READ and WRITE lines, respectively, which, when activated, are placed in UP levels (+). Activating a WRITE CLOCK line writes into the row of cells 2 addressed thereby the data, present on the 32 DATA IN column lines, into the 32-bit locations of the memory word associated with the particular row. Activating a READ line to a row of cells 2 causes the contents of the cells 2 of the particular row, i.e., the memory word, to be placed on the 32 DATA OUT column lines. Hence, a read operation of the memory word of one row can take place simultaneously with a write operation of the memory word of another row, or the read and write operation of the memory word of the same row can occur simultaneously. For conventional RAM applications, the READ and WRITE lines may be addressed with the same address decode with the aid of a gate control network (not shown), e.g., a write gate control for the WRITE lines. An array cell 2 (Fig. 2) has two cascode levels or banks of selectively operable transistor devices T1-T4. In the first level, differential pair T1 and T2 are controlled by the WRITE CLOCK and its complementary counterpar...