Browse Prior Art Database

Cascode-Logic-Implemented Address Circuits

IP.com Disclosure Number: IPCOM000043056D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 4 page(s) / 36K

Publishing Venue

IBM

Related People

Kovach, PS: AUTHOR [+2]

Abstract

The address circuits of an address system are implemented in cascode logic technology. Specific decoder, read and write driver circuits configured in cascode current switch (CCS) networks are described. The circuits optimize performance, physical chip layout and wiring, and are compatible with random-access memories (RAMs) which have arrays of storage cells with similarly configured CCS networks. CCS configured RAM arrays are known; see, for example, the two-port and three-port arrays described in the preceding article. These arrays can also be operated as a conventional array. For multi-port operation, each set of read and write lines (i.e., one set of read lines and one set of write lines for the two-port array, and two sets of read lines and one set of write lines for the three-port array) uses a separate address decoder.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 42% of the total text.

Page 1 of 4

Cascode-Logic-Implemented Address Circuits

The address circuits of an address system are implemented in cascode logic technology. Specific decoder, read and write driver circuits configured in cascode current switch (CCS) networks are described. The circuits optimize performance, physical chip layout and wiring, and are compatible with random- access memories (RAMs) which have arrays of storage cells with similarly configured CCS networks. CCS configured RAM arrays are known; see, for example, the two-port and three-port arrays described in the preceding article. These arrays can also be operated as a conventional array. For multi-port operation, each set of read and write lines (i.e., one set of read lines and one set of write lines for the two-port array, and two sets of read lines and one set of write lines for the three-port array) uses a separate address decoder. For conventional operation, a common address decoder can be used by the read and write line sets with appropriate gating. Each read and write line uses its own separate read and write driver. By way of explanation, the present address system (Fig. 1) is described with a decoder 10 used commonly for the respective sets of read and write drivers 20 and 30, and which addresses the 32-word 32-bit capacity two-port RAM array of the preceding article. For a 32-word capacity, a five-bit (a to e) address decode is used. Decoder 10 has two 3-bit decode circuits 11 and 12, each of which decodes the first three lower order bits a, b, c of the address code, and four 2-bit decode circuits 13-16, each of which decodes the two high-order bits d, e of the address code. The true and complementary forms of the bits a to e are denoted by the + and - prefixes. Circuits 11-16 coact with the drivers 20 (or 30, as the case might be) to address the 32-word address lines 1R, 2R, etc. (or the 32 pairs of write address lines W1-W1', W2- W2', etc.). Circuits 11 and 12 are identically configured, each having three CCS levels and associated pairs of complementary inputs +A and -A, +B and -B, and +C and -C, and having four outputs -A1, -A2, -A3 and -A4. Bits +a, -a, +b, -b are fed to inputs +A, -A, +B, -B, respectively, of circuits 11 and 12; and bits +c and -c are fed to inputs +C and -C, respectively, of circuit 11 and inputs -C and +C, of circuit 12. Circuits 13 to 16 are also identically configured, each having two CCS levels and associated pairs of complementary inputs +D and -D, and +E and -E. Bits +d and -d are fed to inputs +D and -D, respectively, of circuits 13 and 15 and to inputs -D and +D, respectively, of circuits 14 and 16. Bits +e and -e are fed to inputs +E and -E, respectively, of circuits 13 and 14 and to inputs -E and +E, respectively, of circuits 15 and 16. The outputs -A1 to -A4 of circuits 11-12 are connected to the inputs DL of the drivers 20 and 30 and the outputs -ED of the circuits 13-16 are connected to the inputs DH of the drivers 20 and 30, as indicated in

(Image Omit...