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Clocked Magnet Driver

IP.com Disclosure Number: IPCOM000043085D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Renz, W: AUTHOR [+2]

Abstract

A clocked magnet driver circuit is proposed which, owing to its preselected initial attraction and holding currents, is well suited for driving magnets, relays, or the like. The circuit (Fig. 1) consists of a push-pull power output stage with driver transistors Q1, Q2, two flip-flops 1, 2, two comparators 3, 4, and an oscillator 5 of preferably 16 kHz. The special feature of this circuit is that it automatically switches from a relatively high initial attraction current IA to a lower holding current IH. The values of the initial attraction (peak) current IA and the holding (steady-state) current IH are determined as follows by suitably selecting the sense resistor RS and the reference resistors R1, R2, R3, where VCC is the supply voltage: (Image Omitted) The circuit and its function are described in detail by means of Figs.

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Clocked Magnet Driver

A clocked magnet driver circuit is proposed which, owing to its preselected initial attraction and holding currents, is well suited for driving magnets, relays, or the like. The circuit (Fig. 1) consists of a push-pull power output stage with driver transistors Q1, Q2, two flip-flops 1, 2, two comparators 3, 4, and an oscillator 5 of preferably 16 kHz. The special feature of this circuit is that it automatically switches from a relatively high initial attraction current IA to a lower holding current IH. The values of the initial attraction (peak) current IA and the holding (steady-state) current IH are determined as follows by suitably selecting the sense resistor RS and the reference resistors R1, R2, R3, where VCC is the supply voltage:

(Image Omitted)

The circuit and its function are described in detail by means of Figs. 1 and 2. In the standby state, both flip-flops (latches) are set, holding latch 2 by the clock signal of oscillator 5 and peak latch 1 by the inverted input signal. As a non- activated input simultaneously blocks the driver output stages with Ql, Q2, no current IC is permitted to flow through coil 6, shown as an output load. It is only when the input is activated that both driver transistors Q1, Q2 are switched on. Current IC rises until it reaches the preselected initial attraction current IA. It is then that peak latch 1 is reset, after holding latch 2 has been previously reset. Thus, the push-pull driver stage with Q1...