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Browse Prior Art Database

Built-In Facilities to Allow Critical Timing Measurements

IP.com Disclosure Number: IPCOM000043087D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Lechaczynski, M: AUTHOR [+2]

Abstract

This article relates to the measurement of critical timings in a machine, such as a central control unit, by dissociating one cycle from all the others. Thus, particular signals can be viewed dynamically, and the moment when the test case cannot meet the critical timing can be determined. The basic idea is to view the timing on a one-cycle basis, and to implement a built-in steady generator to ease the viewing at oscilloscope. These ideas are implemented in a machine conceived using the so-called level sensitive scan design (LSSD) technique. In such a machine, combinatorial logic performs operations based on input data stored in source latches and the result is stored in a destination latch after a n-logic layer path.

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Built-In Facilities to Allow Critical Timing Measurements

This article relates to the measurement of critical timings in a machine, such as a central control unit, by dissociating one cycle from all the others. Thus, particular signals can be viewed dynamically, and the moment when the test case cannot meet the critical timing can be determined. The basic idea is to view the timing on a one-cycle basis, and to implement a built-in steady generator to ease the viewing at oscilloscope. These ideas are implemented in a machine conceived using the so-called level sensitive scan design (LSSD) technique. In such a machine, combinatorial logic performs operations based on input data stored in source latches and the result is stored in a destination latch after a n-logic layer path. Generally, for a given path only a one-bit change in a given source latch S causes the destination latch status to change. Thus, by changing this bit value, and viewing the destination latch input with an oscilloscope, the n-logic layer path delay can be measured. Instead of feeding that specific source latch by its normal functional input, it is fed in critical timing mode by a signal which is the inverse of the previous status and is short with respect to the cycle time. This is performed through the feedback circuit shown in the drawing. For oscilloscope viewing, no critical timing is needed. The normal timing or an even more relaxed one can be used, and precise measurement of the n-layer...