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Delta-I Noise Reduction in Array Chip Addressing

IP.com Disclosure Number: IPCOM000043091D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Kesselman, JJ: AUTHOR [+2]

Abstract

The effect of the noise generated by the simultaneous switching of signal levels in a circuit arrangement, in which the same signal pattern is replicated (to reduce fanout problems) and distributed to a plurality of components from a single chip, can be reduced by allowing alternately true and complement versions of those signal patterns to drive the components. Those components will respond in a similar fashion for both the true and complement versions of the signal pattern. By allowing multiple copies of true and complement patterns leaving the driving chip, the effective noise level of that chip is reduced, desired fanout is achieved with no additional delay to critical paths, and more efficient use of the driving chip's I/O's results.

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Delta-I Noise Reduction in Array Chip Addressing

The effect of the noise generated by the simultaneous switching of signal levels in a circuit arrangement, in which the same signal pattern is replicated (to reduce fanout problems) and distributed to a plurality of components from a single chip, can be reduced by allowing alternately true and complement versions of those signal patterns to drive the components. Those components will respond in a similar fashion for both the true and complement versions of the signal pattern. By allowing multiple copies of true and complement patterns leaving the driving chip, the effective noise level of that chip is reduced, desired fanout is achieved with no additional delay to critical paths, and more efficient use of the driving chip's I/O's results. The benefits are maximized when there is an even number of true and complement signal patterns emanating from the driving chip. The primary application of this arrangement is in providing addresses for a multi-chip (array) memory configuration, in which an address generator chip provides an n- bit-wide address signal pattern to be distributed to each chip in the memory configuration. As illustrated in Fig. 1, the address generator chip 1 incorporates address generating logic 2 which is applied to a plurality of off-chip driver (OCD) boxes 3, where each box 3 represents n-drivers, each corresponding to a bit in the address signal. As is common, each off-chip driver cycles through a...