Browse Prior Art Database

Early Store-Through of Xi-Sensitive Data

IP.com Disclosure Number: IPCOM000043093D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Knight, JW: AUTHOR [+2]

Abstract

The disclosed mechanism reduces the frequency of cast-outs caused by references to data shared by central processing units (CPUs) in a multiprocessor (MP) configuration. In tightly-coupled MP systems the CPUs may compete for data. When a CPU issues, e.g., a store request, the system needs to insure that the other CPUs do not occupy the involved cache line. Upon such a store, if the requesting CPU does not own the cache line exclusively (indicated by a status bit in the cache), the directories of other CPUs need to be searched and the cache line found in any other CPU will be invalidated. Such phenomenon is called cross-interrogates (XIs). In case the cache line invalidated through an XI happens to have been modified, the line usually needs to be cast-out to a shared memory and then fetched to the requesting CPU.

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Early Store-Through of Xi-Sensitive Data

The disclosed mechanism reduces the frequency of cast-outs caused by references to data shared by central processing units (CPUs) in a multiprocessor (MP) configuration. In tightly-coupled MP systems the CPUs may compete for data. When a CPU issues, e.g., a store request, the system needs to insure that the other CPUs do not occupy the involved cache line. Upon such a store, if the requesting CPU does not own the cache line exclusively (indicated by a status bit in the cache), the directories of other CPUs need to be searched and the cache line found in any other CPU will be invalidated. Such phenomenon is called cross-interrogates (XIs). In case the cache line invalidated through an XI happens to have been modified, the line usually needs to be cast-out to a shared memory and then fetched to the requesting CPU. XIs are subject to performance penalties, especially when the cache size grows and when the number of CPUs increases. Among the XIs the XI cast-outs are most costly. XI activities tend to concentrate on a limited category of data in the software system. Such XI- sensitive data consist of certain pointers, control blocks and locks in the operating systems or subsystems. They may be identified by appropriate tagging of the XI histories. XI cast-out penalties may be reduced if the modifications to such XI-sensitive data are stored-through early to the memory. The proposed mechanism allows to identify XI-sensitive data and do early store-throughs. Store-in first level caches (L1) are considered. The XI-sensitivity marking scheme in cache directories is first described. Let us assume the existence of a second level cache (L2) which may or may not be shared by the CPUs in the MP configuration. Let us assume also that each entry of the cache (L1 and L2) directories is enhanced with a bit called the X-bit. The X-bits are used to keep track of the past XI histories of the lines. W...