Browse Prior Art Database

Segmented Virtual to Real Translation Assist

IP.com Disclosure Number: IPCOM000043095D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Knight, JW: AUTHOR [+2]

Abstract

Translation of a range of contiguous virtual addresses to a range of contiguous real addresses is performed through appropriate registers and instructions to manipulate these registers without reference to the translation look-aside buffer (TLB) or page and segment tables. For terms and features referred to in this article reference is made to IBM System/37, Principles of Operation, GA22-7000. A Set Translation Range (STRG) instruction of the S format is provided to enable the control program to indicate that contiguous virtual to real mapping is to apply in a particular range or ranges. The contents of storage at the second operand address specify the contiguous virtual address range(s) and corresponding real address range(s).

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Segmented Virtual to Real Translation Assist

Translation of a range of contiguous virtual addresses to a range of contiguous real addresses is performed through appropriate registers and instructions to manipulate these registers without reference to the translation look-aside buffer (TLB) or page and segment tables. For terms and features referred to in this article reference is made to IBM System/37, Principles of Operation, GA22-7000. A Set Translation Range (STRG) instruction of the S format is provided to enable the control program to indicate that contiguous virtual to real mapping is to apply in a particular range or ranges. The contents of storage at the second operand address specify the contiguous virtual address range(s) and corresponding real address range(s). The validity of the translation (segment and page table entries) is checked and the information retained and used to translate subsequent reference to virtual addresses in the specified range(s). In a simple implementation, only one range of addresses is translated and the information at the second operand address of a STRG instruction is interpreted as a pair of virtual addresses and a pair of real addresses for a total of four 32-bit words. The addresses would be interpreted as page addresses, the least significant eleven (2K pages) or twelve (4K pages) bits being ignored. The difference between the first and last virtual address and the first and last real address, ignoring the low- order bit...