Browse Prior Art Database

XOR Randomization in Cache Congruence Class Indexing

IP.com Disclosure Number: IPCOM000043106D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

The technique disclosed in this article reduces cache misses that are caused by special collision situations through randomization on congruence class selection. Many high end processors are designed with tightly-coupled dyadic configurations. Although such processors are mainly intended to run jobs under the control of single operating systems, there is potential that separate operating systems may run on different CPUs. When similar, but separate, operating systems are used in a shared cache, certain congruence classes may have heavy replacement activities. For instance, instruction lines from busy multiple virtual storage (MVS) modules, like Dispatcher and Getmain/Freemain, may be indexed to the same group of second level cache (L2) congruence classes if the memories used by the two systems are separated improperly, e.g.

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XOR Randomization in Cache Congruence Class Indexing

The technique disclosed in this article reduces cache misses that are caused by special collision situations through randomization on congruence class selection. Many high end processors are designed with tightly-coupled dyadic configurations. Although such processors are mainly intended to run jobs under the control of single operating systems, there is potential that separate operating systems may run on different CPUs. When similar, but separate, operating systems are used in a shared cache, certain congruence classes may have heavy replacement activities. For instance, instruction lines from busy multiple virtual storage (MVS) modules, like Dispatcher and Getmain/Freemain, may be indexed to the same group of second level cache (L2) congruence classes if the memories used by the two systems are separated improperly, e.g., by 16 megabytes. The problem may be solved through XOR randomization in cache congruence class indexing. The technique is described with reference to an L2 of 1 megabyte having 1024 congruence classes with four lines in each congruence class. The L2 line size is 256 bytes. The congruence class of a reference is selected using bits 14-23 of the real address of the reference. If two MVS systems have disjoint memory locations allocated to the individual systems, corresponding lines of the nucleuses (e.g., a line in Dispatcher) of these two systems will be contained in the same congruence class...