Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Multiple Byte-Length Units

IP.com Disclosure Number: IPCOM000043109D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Becker, GC: AUTHOR [+3]

Abstract

Many programmable units (microprocessor and microcomputer chips) use a parity bit along with 8 bits of data on their internal data buses to afford a checking mechanism for the data. Other programmable units use an 8-bit bus without parity. To combine checking mechanisms into a unit that has an 8-bit data bus without parity, the data passed through the unit is coded to employ 7 data bits plus a coded parity bit (7+CP). This coded parity bit, CP, is generated with the 7 bits of data in a functional microcode load. To match the 7+CP bus with the 8+HP (hardware generated parity) bus which runs between the various control functions, additional circuits external to the programmable unit generate an additional parity bit to yield 7+CP+HP.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 67% of the total text.

Page 1 of 2

Multiple Byte-Length Units

Many programmable units (microprocessor and microcomputer chips) use a parity bit along with 8 bits of data on their internal data buses to afford a checking mechanism for the data. Other programmable units use an 8-bit bus without parity. To combine checking mechanisms into a unit that has an 8-bit data bus without parity, the data passed through the unit is coded to employ 7 data bits plus a coded parity bit (7+CP). This coded parity bit, CP, is generated with the 7 bits of data in a functional microcode load. To match the 7+CP bus with the 8+HP (hardware generated parity) bus which runs between the various control functions, additional circuits external to the programmable unit generate an additional parity bit to yield 7+CP+HP. The microcode addressing structure and hardware are used to differentiate between the two data formats that can be passed through the programmable units. The address of the targeted control function that is to receive or send data determines whether 7 or 8 bits of data are sent. When the transfer of data is determined to be coming from a programmable unit in the form of 7+CP, the parity across the 7 bits of data is immediately checked as it leaves the programmable unit and as well as at its destination. The dual checking operates on the internal bus structures and some of the internal registers within programmable units which do not have their own internal checking. Likewise, data sent back from control funct...