Browse Prior Art Database

Input/Output Channel Address Assignment Mechanism

IP.com Disclosure Number: IPCOM000043113D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Bourke, DG: AUTHOR [+5]

Abstract

A channel address is described that may be applied to any 32-bit multiplexed Address/Data I/O channel architecture. The requirements of an acceptable implementation are: 1. Provide for 32 logical I/O channel addresses. 2. Provide for greater than 32 physical I/O channel positions. 3. Provide for physical addressing and logical address assignment of I/O channels. 4. Provide for logical addressing and physical identification of I/O channels (for servicing and replacement). 5. Allow broadcast summary read operations that identify up to 32 logical I/O channels with a single command. 6. Provide a common design for the I/O channels that requires minimum board wiring and I/O pins. This proposal meets all of the requirements listed above.

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Input/Output Channel Address Assignment Mechanism

A channel address is described that may be applied to any 32-bit multiplexed Address/Data I/O channel architecture. The requirements of an acceptable implementation are: 1. Provide for 32 logical I/O channel addresses. 2. Provide for greater than 32 physical I/O channel positions. 3. Provide for physical addressing and logical address

assignment of I/O channels. 4. Provide for logical addressing and physical identification of I/O channels (for servicing and

replacement). 5. Allow broadcast summary read operations that

identify up to 32 logical I/O channels with a

single command. 6. Provide a common design for the I/O channels that requires minimum board wiring and I/O pins. This proposal meets all of the requirements listed above. Implementation of this proposal requires each board terminator/repower card to have four jumper positions from Address/Data (A/D) bus bits 9, 10, 11 and 12 to a common driver input (Fig. 1). The driver output is the Board Select (B/S) line for the card file. The terminator/repower cards will each have a single jumper installed so that the first card file has its board select line active whenever A/D bus bit 9 is active, the second card file has its board select line active whenever A/D bus bit 10 is active, etc. Each I/O channel attachment card receives the B/S line on a common I/O pin. Each I/O channel attachment card receives and drives a Card Select (C/S) line on a common I/O pin. The C/S lines are unique connections to an A/D bus line (16-31) via board wiring for each I/O card position on the board. Fig. 2 shows the Intermediate Control Block (ICB) contents for three I/O commands required by this proposal. When the Command (CMD) Bus is set equal to the code points assigned for these commands, the A/D bus will have the contents of the ICB words shown for the Address Select (ASEL) and Data Select (DSEL) cycles. The "Set Logical I/O Channel Address" command uses one of the A/D bus bits 9-12 to select one of four boards and one of the A/D bus bits 16-31 to select one of sixteen cards on the board. The card that is physically selected loads the A/D bus bits 4-8 into its logical channel address (LCA) register.

Fig. 3 is a diagram of the logic required for each I/O channel attachment....