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CVS One-Device Cell Masterslice

IP.com Disclosure Number: IPCOM000043116D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+4]

Abstract

A masterslice image is provided for cascode voltage switch (CVS) logic circuits, either of the differential or single-ended type. A clocked differential CVS logic circuit which may be formed in this masterslice image is illustrated in Fig. 1 and a clocked single-ended CVS logic circuit which may also be formed in this masterslice image is described in [*]. As can be seen, the single-ended CVS logic circuit is essentially one-half of the differential CVS logic circuit. The clocked differential CVS logic circuit in Fig. 1 includes transistors T1, T7 and T6, T8 which form output buffers, transistors T3, T4 and T9 which are used as precharge devices, and transistors T2 and T5 which are feedback devices. Disposed between precharge device T9 and precharge devices T3 and T4 is a combination network which may be of any known type.

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CVS One-Device Cell Masterslice

A masterslice image is provided for cascode voltage switch (CVS) logic circuits, either of the differential or single-ended type. A clocked differential CVS logic circuit which may be formed in this masterslice image is illustrated in Fig. 1 and a clocked single-ended CVS logic circuit which may also be formed in this masterslice image is described in [*]. As can be seen, the single-ended CVS logic circuit is essentially one-half of the differential CVS logic circuit. The clocked differential CVS logic circuit in Fig. 1 includes transistors T1, T7 and T6, T8 which form output buffers, transistors T3, T4 and T9 which are used as precharge devices, and transistors T2 and T5 which are feedback devices. Disposed between precharge device T9 and precharge devices T3 and T4 is a combination network which may be of any known type. P channel devices are identified by the letter P, and N channel devices are identified by the letter N. Fig. 2 illustrates the masterslice image in which the circuit of Fig. 1 may be formed. The masterslice image includes a power bus VH and a ground bus GND formed on a layer of insulation 10, such as silicon dioxide, which may be grown on a semiconductor substrate 12 made of P type conductivity. A guard ring made of a heavily doped N type impurity is formed within substrate 12 between the power bus VH and the ground bus GND. An N well is located in substrate 12 between power bus VH and the guard ring, and the P channel devices, such as transistors T1-T6, are formed therein by any known technique. The combinational network, which includes exclusively N channel devices, is formed in substrate 12 between the guard ring and ground bus GND. The combination network area in the masterslice image includes a plurality of one-device cells 14 arranged in rows and columns. As illustrated in Fig. 2, each row contains four one-device cells and each column contains six one-device cells. Each cell 14 includes an N+ source region S and an N+ drain region D between which is disposed a control gate G insulated from substrate 12 by insulting layer 10. Control gate G is preferably made of doped polysilicon and is covered by a layer...