Browse Prior Art Database

Fast Directory Invalidation

IP.com Disclosure Number: IPCOM000043117D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Blascheck, WD: AUTHOR [+4]

Abstract

For the simultaneous invalidation of all lines in a set-associative directory, each line is provided with a common validity bit (CVB) implemented as a latch in an array of latches which can be reset in one cycle. Fig. 1 shows a conventional four-set-associative directory 2 which is used as a fast translation look-aside buffer for transforming virtual addresses (in register 1) to real addresses (in register 5). Each line 2a of the directory contains the high-order bits VAi of four virtual addresses with the conventional validity bits Vi and the corresponding four real addresses RAi . The directory is physically implemented as a conventional random-access storage.

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Fast Directory Invalidation

For the simultaneous invalidation of all lines in a set-associative directory, each line is provided with a common validity bit (CVB) implemented as a latch in an array of latches which can be reset in one cycle. Fig. 1 shows a conventional four-set-associative directory 2 which is used as a fast translation look-aside buffer for transforming virtual addresses (in register 1) to real addresses (in register 5). Each line 2a of the directory contains the high-order bits VAi of four virtual addresses with the conventional validity bits Vi and the corresponding four real addresses RAi . The directory is physically implemented as a conventional random-access storage. In operation, part of the virtual address in register 1 is supplied as a line address on bus 7 to the directory for reading all of the four stored virtual addresses which are then compared in compare circuits 3 with the high-order part of the virtual address supplied on bus 9. If one of the stored virtual addresses matches the supplied virtual address, the corresponding real address is selected by AND circuits 4 and OR circuit 4a and concatenated to the part of the virtual address (on bus 10) which does not require translation. Occasionally, the whole contents of directory 2 must be invalidated, for instance, upon a task change during multiprocessing. Resetting of the individual validity bits Vi would require one machine cycle for each directory line. For increased speed, it is proposed to logically supplement the directory by one CVB for each line, th...