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Design and Structure for 32-Bit Barrel Shifter

IP.com Disclosure Number: IPCOM000043124D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 4 page(s) / 94K

Publishing Venue

IBM

Related People

Cook, PW: AUTHOR [+2]

Abstract

This article describes a 32-bit barrel shifter, which, together with an arithmetic logic unit and a register file, forms the data path of a general processor machine. The barrel shifter macro consists of a pass transistor array, input and output drivers, and decoder circuitry for selecting and driving the pass transistor gates. The shifter described herein is designed for 32 bits, and can rotate 32-bit wide data from 0 to 3l bit positions in a nominal delay of a few nanoseconds. Depending on the "base" used to implement the shifter, the pass transistor array may be divided into two or more stages in order to save area at some cost in delay. The three-stage implementation appears to offer the most efficient use of area for a slight delay penalty relative to the one-stage implementation which gives the least delay.

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Design and Structure for 32-Bit Barrel Shifter

This article describes a 32-bit barrel shifter, which, together with an arithmetic logic unit and a register file, forms the data path of a general processor machine. The barrel shifter macro consists of a pass transistor array, input and output drivers, and decoder circuitry for selecting and driving the pass transistor gates. The shifter described herein is designed for 32 bits, and can rotate 32-bit wide data from 0 to 3l bit positions in a nominal delay of a few nanoseconds. Depending on the "base" used to implement the shifter, the pass transistor array may be divided into two or more stages in order to save area at some cost in delay. The three-stage implementation appears to offer the most efficient use of area for a slight delay penalty relative to the one-stage implementation which gives the least delay. The delay considered herein is with respect to the data input, not the control lines which set up the shift path; the latter delay may be longer but may not limit the data path delay.

If the addresses for the shift count are available before the data appears at the inputs of the barrel shifter, then the delay through the shifter is probably the limiting parameter. If, though, the data and the addresses both become valid at the same time, then the total delay is the sum of the time needed to decode the addresses and set-up the control lines and the time needed to propagate a bit from the input to the output of the shifter. The present description considers the optimal design of the path through the shifter assuming that the control signals are already present. A parametrized design approach was used in designing the 32-bit shifter. The parameters that characterize a barrel shifter are: 1) Number of bits of data word, M; 2) Base, B;

3) Number of stages, n;

4) Placement order of the stages;

5) Layout configuration of the pass transistors;

6) Size of the pass transistor;

7) Size of the input driver;

8) Size of the output driver. For a given M, the other parameters listed should be chosen based on considerations of speed, power, and the use of silicon area. The example in this article describes the procedure used to select a set of parameters that optimizes the speed performance of the 32-bit shifter (M=32). Fig. 1 shows a schematic of a three-stage implementation of a 32-bit barrel shifter. Note that at each stage, a wire-folding technique has been applied to reduce the number of wires needed to direct each input data bit through the appropriate pass transistor shift path. Fig. 2 shows a schematic representation of the path through the barrel shifter which is seen for one bit. It consists of an input inverter, a pass transistor chain which represents the data shift path, and an output inverter. Each transistor can be considered as (1) a series resistance in the carry path, (2) a capacitance to ground formed by the gate-to-channel capacitance of each transistor, and (3) the strays...