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Algorithm for Deducing the Logical Behavior of Arbitrary FET Circuits

IP.com Disclosure Number: IPCOM000043133D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 8 page(s) / 53K

Publishing Venue

IBM

Related People

Pfister, GF: AUTHOR

Abstract

The problem addressed is: Given an FET network, create a functional description of the logic it realizes in terms of traditional switching algebra gates (or equations) and storage elements. The algorithm presented here, called the connection algorithm, creates such a description of an arbitrary FET network's outputs in terms of its inputs, where the values assumed by inputs and outputs are binary: l denotes the presence, and 0 the absence, of sufficient charge to switch a transistor. The binary values appearing on internal network nodes are not necessarily described, but if desired, they can be. Applications of the connection algorithm include the design, simulation, and logical-to-physical checking of VLSI FET networks 1.

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Algorithm for Deducing the Logical Behavior of Arbitrary FET Circuits

The problem addressed is: Given an FET network, create a functional description of the logic it realizes in terms of traditional switching algebra gates (or equations) and storage elements. The algorithm presented here, called the connection algorithm, creates such a description of an arbitrary FET network's outputs in terms of its inputs, where the values assumed by inputs and outputs are binary: l denotes the presence, and 0 the absence, of sufficient charge to switch a transistor. The binary values appearing on internal network nodes are not necessarily described, but if desired, they can be. Applications of the connection algorithm include the design, simulation, and logical-to-physical checking of VLSI FET networks 1. ÙThe connection algorithm described herein is general, in the sense that it can be used to create a logical description of any FET network, including bidirectional pass-transistor networks and networks employing stored charge. Restrictions As presented here, the connection algorithm only operates on FET networks that are electrically isolated, i.e.: ...All primary network inputs connect only to transistors' gates. ...All primary network outputs are assumed to terminate at transistors' gates outside the network. ...Aside from such designated inputs and outputs, there are no other connections to the network except for power (Vdd) and ground. The connection algorithm makes the following assumptions: ...Switchable FET devices act as perfect switches, i.e., they have either 0 or infinite impedance depending on the charge on their gate inputs. ...Depletion-mode transistors, and similar devices used as resistors, have very high impedance compared to the "on" impedance of a switchable transistor, and a very low impedance compared to the "off" impedance. The impedance of such devices is otherwise not considered known. Under these assumptions, there exist FET networks whose behavior is not well-defined for one or more sets of input values. For example, consider Fig. 1. If (A,B) = (1,0), X is 1; if (A,B) = (0,1), X is 0. However, when (A,B) is either (0,0) or (1,1), X's value is undefined. To handle such cases, the connection algorithm adds to the logic description additional outputs called error outputs . These are 1 if and only if one or more signals in the network are not well defined, e.g., are midway between a power-to-ground voltage divider composed of two resistive devices. For the example of Fig. 1, an error output would be created which would implement the inverse of an exclusive-OR of A and B. In most cases, error output values of 1 can be considered indicators of design errors. For convenience, only NMOS FETs will be considered in the description that follows. Obvious extensions extend it to CMOS, etc. Pre-Processing Prior to applying the connection algorithm proper, the FET network must be defined and an initial segmentation step performed. I...