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Improved Gate Model of Dynamic FET Networks

IP.com Disclosure Number: IPCOM000043134D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 5 page(s) / 48K

Publishing Venue

IBM

Related People

Pfister, GF: AUTHOR

Abstract

Given an FET (field-effect transistor) network consisting of nodes connected by FET transistors, suppose a node A has been connected to Vdd, and a node B to ground, and then they are disconnected from Vdd and ground and connected to each other. The values they then take on depend on their relative capacitances, Ca and Cb, as follows: Ca >> Cb both nodes become 1 Ca >> Cb both nodes become 0 Ca = Cb both nodes become "undefined", or an error has occurred. This phenomenon is called charge sharing; FET networks making use of it are referred to as dynamic, rather than static. The algorithm presented here provides an approximate gate model of charge sharing in dynamic FET networks. The present algorithm produces the logic shown in Fig. 1 which handles both simple memory and charge sharing.

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Improved Gate Model of Dynamic FET Networks

Given an FET (field-effect transistor) network consisting of nodes connected by FET transistors, suppose a node A has been connected to Vdd, and a node B to ground, and then they are disconnected from Vdd and ground and connected to each other. The values they then take on depend on their relative capacitances, Ca and Cb, as follows: Ca >> Cb both nodes become 1 Ca >> Cb both nodes become 0 Ca = Cb both nodes become "undefined", or an error has occurred. This phenomenon is called charge sharing; FET networks making use of it are referred to as dynamic, rather than static. The algorithm presented here provides an approximate gate model of charge sharing in dynamic FET networks. The present algorithm produces the logic shown in Fig. 1 which handles both simple memory and charge sharing. The box labelled "CS logic" is defined subsequently; the inputs M and "normal value" are defined in the preceding article, and "actual value" is the next value taken on by the node modelled by the present logic. While the amount of logic created by this technique is related to the square of the number of nodes which can share charge, it can be reduced to very few gates for common cases. The algorithm proceeds in two stages: 1. Each segment is divided into sub-networks which can potentially share charge with each

other. 2. Logic is constructed for each sub-network to

model the effect of charge sharing on it. These two steps are described below. First, however, the electrical and algebraic bases of the technique are presented. The actual value produced by charge sharing is defined using conservation of charge. Let Ci be the capacitance of each node i, and Qi be the charge initially on each node i. Then after charge sharing, a group of connected nodes will have the same voltage V defined by: V = S(Qi) / S (Ci) where the sums are overall connected nodes of the group. Equivalently, let Vi be the voltage on each node i just prior to the start of charge-sharing. Then since Qi=Vi*Ci, we have V = S(Vi*Ci) / S(Ci) Whether V is a logical 1 or 0 is determined by comparing it to the switching threshold Tj (relative to ground) of each transistor j to whose gate it is applied. V<Tj means V is a l; V<Tj means V is a 0. If V=Tj, the result is undefined in a logical sense. If it is assumed that FETs are perfect switches (impedance = 0 or infinity only), then the voltage at every node in the network is either Vdd or 0 (i.e., there are no source-drain threshold drops). Let PVi stand for "the logical value of node i just prior to the start of charge-sharing." Then the convention used means that: Vi = 0 when PVi = 0 Vi = Vdd when PVI = 1 This means that there is single threshold T relative to ground which is the same for every transistor, equal to the local gate-source threshold. This threshold T is related to the supply voltage simply: T = f*Vdd where 0<f<1 (always) and typically 0.2<f<0.3. Then the logical value assumed by a g...