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Algorithm for Modelling "Stuck at" Faults for Fault Simulation

IP.com Disclosure Number: IPCOM000043135D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Kronstadt, EP: AUTHOR

Abstract

The "coverage" associated with a set of tests applied to hardware parts at manufacture gives a good indication of how good the tests are as measures of whether the tested part will work. Generally this coverage is obtained by applying the tests to a simulated model of the part in which every "possible" fault is inserted, one fault at a time. This procedure is called "fault simulation." The coverage obtained from fault simulation is defined to be the percentage of these faults that are detected by the tests. The coverage is clearly dependent on the model used for describing faults. A model frequently used is the "stuck fault" model, in which a fault is defined as the output or input of a gate being "stuck at" 0 (logical 0) or 1 (logical 1).

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Algorithm for Modelling "Stuck at" Faults for Fault Simulation

The "coverage" associated with a set of tests applied to hardware parts at manufacture gives a good indication of how good the tests are as measures of whether the tested part will work. Generally this coverage is obtained by applying the tests to a simulated model of the part in which every "possible" fault is inserted, one fault at a time. This procedure is called "fault simulation." The coverage obtained from fault simulation is defined to be the percentage of these faults that are detected by the tests. The coverage is clearly dependent on the model used for describing faults. A model frequently used is the "stuck fault" model, in which a fault is defined as the output or input of a gate being "stuck at" 0 (logical 0) or 1 (logical 1). The success of this model in large numbers of actual hardware parts has made the question of how close the model "reflects reality" somewhat moot. However, the stuck fault model has only been applied to hardware that is designed in terms of standard logic gates (ANDs, ORs, etc.) The present algorithm deals with FET circuits in which pass transistor logic has been used to perform functions in a way that cannot be closely modelled in logic gates. In this case a stuck fault model can be extended to the FET circuits: either the nodes in the circuit can be "stuck at l" or "stuck at 0," or the transistors in the circuits can be "stuck on" or "stuck off." The problem arises in performing the fault simulation: how to model the stuck node, and how to insert the faults? This algorithm presents solutions to these problems. The method consists of a simple modification of the techniques described on pages 1168-1179 of this issue In that article, a method (called the "connection algorithm") for transforming an arbitrary FET network into an equivalent logic gate description for the purposes of simulation is described. It would make little sense to "stick" the outputs or inputs of the gates in the resulting description, since few, if any, of the logic gates used to describe a large-pass transistor network would correspond to the actual nodes or transistors in the network. In order to build the stuck-fault mode, one adds additional circuitry to the original description of the FET circuit...