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Manchester Code Encoder Circuit

IP.com Disclosure Number: IPCOM000043173D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Nahata, P: AUTHOR

Abstract

The primary purpose of this encoder circuit is to reduce the number of circuit components normally required in an encoder of this type. Manchester code encoding operation requires that when consecutive ones or consecutive zeros are to be transmitted, crossover bits must be introduced in the transmission stream. A decoder at the receiving end will recondition the data to its original form. The basic principal of operation of this circuit is based on the "look ahead" method. The data bit to be transmitted at the next clock cycle is compared with the data bit ready for transmission. If both data bits are of the same polarity, then a crossover bit is introduced. No crossover bit is introduced if both bits are of opposite polarity. In the circuit shown in Fig. 1, Q1 represents the data bit to be transmitted.

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Manchester Code Encoder Circuit

The primary purpose of this encoder circuit is to reduce the number of circuit components normally required in an encoder of this type. Manchester code encoding operation requires that when consecutive ones or consecutive zeros are to be transmitted, crossover bits must be introduced in the transmission stream. A decoder at the receiving end will recondition the data to its original form. The basic principal of operation of this circuit is based on the "look ahead" method. The data bit to be transmitted at the next clock cycle is compared with the data bit ready for transmission. If both data bits are of the same polarity, then a crossover bit is introduced. No crossover bit is introduced if both bits are of opposite polarity. In the circuit shown in Fig. 1, Q1 represents the data bit to be transmitted. Q2 represents the data bit to be transmitted at the next clock cycle. Two separate timing clocks are required for the operation of the circuit: one as a data clock and the other as a clock operating at twice the speed of the data clock, as shown in the timing diagram of Fig. 2. At timing period 1, both Q1 and Q2 have opposite polarity; therefore, no crossover bit is introduced. At timing period 2, the data bits have an opposite polarity, and again no crossover bit is introduced. At clock period 3, the data bits have the same polarity; therefore, a crossover bit must be introduced in the transmission stream. This is accomplished by a...