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Programmable Logic Array

IP.com Disclosure Number: IPCOM000043179D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Beha, H: AUTHOR

Abstract

Using a personalized two-input phase splitter to provide the true and complement functions of each input signal, and controlling the driver gates vertically through the array, provides high performance and high density and simple personalization. Figs. 1 and 2 show the three basic blocks of a DC-powered Josephson programmable logic array (JPLA). The phase splitter circuit provides the true and complement functions of each input signal. In order to achieve a higher logic functionality, a personalized two-input phase splitter circuit can be used instead of a one-input signal phase splitter circuit. The true and the negated (X and X input signals control the driver gates for the control lines running vertically through the AND array. The input signals are delivered to the AND plane.

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Programmable Logic Array

Using a personalized two-input phase splitter to provide the true and complement functions of each input signal, and controlling the driver gates vertically through the array, provides high performance and high density and simple personalization. Figs. 1 and 2 show the three basic blocks of a DC- powered Josephson programmable logic array (JPLA). The phase splitter circuit provides the true and complement functions of each input signal. In order to achieve a higher logic functionality, a personalized two-input phase splitter circuit can be used instead of a one-input signal phase splitter circuit. The true and the negated (X and X input signals control the driver gates for the control lines running vertically through the AND array. The input signals are delivered to the AND plane. The AND/OR arrays are essentially read-only memory (ROM)- arrays, where the ROM cells can be personalized either by changing a single mask or using a laser technique. In the AND array the wordline (also called product term line), consisting of galvanically in-series connected ROM cells, runs horizontally through the AND array and controls at the end of the array the non- inverting interface gate QI to the OR array. In the AND array the input signals and their negated signals are selectively connected to product term lines in such a way that certain combinations of input signals produce the logically true signal "1" of one or more product term lines, i.e., at the AND/OR array interface gates QI . The output lines of the interface gates are input to the OR array, where other selecting connections to the ROM cells of the OR plane transfer finally the signals to the output register gates; i.e., the OR array performs the sum of the product terms. Hence, the logic functions of the AND/OR arrays are NOR, so that the JPLA corresponds to a two-level N...