Browse Prior Art Database

Programmable Algorithmic Skip and Redundancy Packing Feature

IP.com Disclosure Number: IPCOM000043181D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Anemojanis, E: AUTHOR [+2]

Abstract

This new approach of testing memory circuits with redundancy enables us to maximize the throughput of any memory test system. Presently this is performed in software which requires large memory space both in the tester and computer. This hardware-implemented logic function initiates a skip to the next device at the instant the device under test (DUT) fails the selected criteria. OPERATION SET UP The part number program LD (PNP) loads the I/O program register 5, the single-cell program register 20, the word line program register 2, the device program register 3, the word fail counter 4 and the I/O fail counter 11. The SAR (storage address register) counter 8 is loaded with the last address number of the device. The word line program register 2 is loaded with the number of redundant lines per circuit.

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Programmable Algorithmic Skip and Redundancy Packing Feature

This new approach of testing memory circuits with redundancy enables us to maximize the throughput of any memory test system. Presently this is performed in software which requires large memory space both in the tester and computer. This hardware-implemented logic function initiates a skip to the next device at the instant the device under test (DUT) fails the selected criteria. OPERATION SET UP The part number program LD (PNP) loads the I/O program register 5, the single-cell program register 20, the word line program register 2, the device program register 3, the word fail counter 4 and the I/O fail counter 11. The SAR (storage address register) counter 8 is loaded with the last address number of the device. The word line program register 2 is loaded with the number of redundant lines per circuit. The single-cell program register 20 is loaded with the maximum allowable single-cell fails on different word lines. The I/O program register 5 is loaded with the I/O fail limit. It should be noted that the SAR counter 8 is used during the data transfer mode to the CPU. In the product test mode, the pattern generator address is selected through the multiplexer 6. The redundancy memory 21, and the single-cell memory 22 are cleared and everything is preset by using SAR counter 8. Any fail data from the device under test (DUT) (not shown) is strobed in the fail data register 9 which is compared at all times with the output of the redundancy memory DO 21 by comparator 10. A fail bit on any I/O will force a "write 1" into the associated redundancy memory I/O location. The output of the comparator 10 decrements the I/O fail counter 11. The outputs of the I/O fail counter's address programmable read only memory (PROM) 12 which is always compared with the I/O programmed value register 5 at comparator 13. The output of the I/O comparator 13 can be gated to the circuit fail latch 18 through multiplexer 23. The same applies to the word line PROM 16 which is compared to the programmed value of register 2 at comparator 17. The selection of the three inputs of multiplexer 23 are product-type dependent and are programmed in the part number program (PNP) as shown below: - Input A for any product * Without redundancy and

* Partial sorting in I/O dimension - Input B...