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Compact One-Device Dynamic RAM Cell With High Storage Capacitance

IP.com Disclosure Number: IPCOM000043192D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is described for making compact one-device dynamic RAM (random-access memory) cells. The right side of Fig. 11 depicts the cross-section of the one-device cell resulting from this method. Fig. 12 shows the top view of a 2 x 2 cross-section of the RAM array. As these two figures illustrate, the entire one-device cell is contained within the confines of a single well-like trench whose horizontal dimensions would typically be 2 x 2 mm2, assuming "2 mm" lithography as the state of the art. In Fig. 11, the N-channel field-effect transistor (FET) of the one-device cell is formed vertically at all four walls of the trench by N+ 6 diffusion and N 16 diffusion as drain/source, respectively; P polysilicon 32 and SiO2 30 form the gate and gate oxide, respectively.

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Compact One-Device Dynamic RAM Cell With High Storage Capacitance

A method is described for making compact one-device dynamic RAM (random- access memory) cells. The right side of Fig. 11 depicts the cross-section of the one-device cell resulting from this method. Fig. 12 shows the top view of a 2 x 2 cross-section of the RAM array. As these two figures illustrate, the entire one- device cell is contained within the confines of a single well-like trench whose horizontal dimensions would typically be 2 x 2 mm2, assuming "2 mm" lithography as the state of the art. In Fig. 11, the N-channel field-effect transistor (FET) of the one-device cell is formed vertically at all four walls of the trench by N+ 6 diffusion and N 16 diffusion as drain/source, respectively; P polysilicon 32 and SiO2 30 form the gate and gate oxide, respectively. The high storage capacitance for the one-device cell is provided by the sum of two capacitances, viz. (1) the "MOS" capacitance between P silicon 22 and N 16 across the thin layers of SiO2 18 and Si3N4 20, and (2) the junction capacitance between N 16 and the surrounding P 2. These two capacitances are present at all four walls of the well-like trench, and each of these capacitances is high by itself because of the depth of the trench. As illustrated in Figs. 11 and 12, metal lines 38 provide the word lines to which FET gates P 32 are connected. N+ diffusion lines 6 provide the bit lines. P 2 and 22 receive a fixed negative bias. The left side of Fig. 11 illustrates an FET of the "conventional" kind which is simultaneously formed by the disclosed method. These FETs provide the basic component for the peripheral circuitry of the RAM. The method preferably starts with a P substrate 2 of moderately high to high concentration, at the surface of which a P- epitaxial layer 4 of approximately 2 mm thickness and moderately low to low concentration is grown. This preferred manner of obtaining two P regions of different concentrations serves to maximize the junction capacitance component of the cell storage capacitance while maintaining the threshold voltage of the cell and peripheral FETs appropriately one volt. Alternatively, one could start with a P substrate 2 of appropriately compromised concentration and skip formation of a P epitaxial layer 4 altogether. Shallow N+ skin regions 6 are next formed using masking and, preferably, arsenic ion implantation across a thin screen SiO2 which has been previously formed at the silicon surface. Drive-in of the Nimpurity is avoided at this stage since subsequent heat cycles will provide the drive-in. The rest of the processing is as follows: 1. Form about a 200- nanometer SiO2 layer 8, about a 100-nanometer Si3N4 layer 10 and about an 800-nanometers SiO2 layer 12 successively at the wafer surface to form Fig. 1.
2. Using photoresist and masking, etch SiO2 layer 12. The known technique of "image transfer" (or "multilayer resist") may be preferred while anisotropic RIE (reac...