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Data Bus Sense Amp With Switched Isolators

IP.com Disclosure Number: IPCOM000043196D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Plass, DW: AUTHOR

Abstract

This is an FET dynamic circuit design which amplifies a small differential signal on a pair of high capacitance data lines rapidly into a full voltage scale signal on low capacitance data lines. It consists of a sense amp, incorporating a novel switched isolator for speed, and a logic circuit to discharge the zero side of the high capacitance lines. The circuit is intended to be used as an I/O Logic Circuit. In this application, the high capacitance lines are I/O and I/O which go through the array to access the bit lines. After I/O sensing, the line that remains high must stay above the supply voltage minus a threshold voltage, and the line going low must discharge to ground potential before the wordline in the array can be turned off.

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Data Bus Sense Amp With Switched Isolators

This is an FET dynamic circuit design which amplifies a small differential signal on a pair of high capacitance data lines rapidly into a full voltage scale signal on low capacitance data lines. It consists of a sense amp, incorporating a novel switched isolator for speed, and a logic circuit to discharge the zero side of the high capacitance lines. The circuit is intended to be used as an I/O Logic Circuit. In this application, the high capacitance lines are I/O and I/O which go through the array to access the bit lines. After I/O sensing, the line that remains high must stay above the supply voltage minus a threshold voltage, and the line going low must discharge to ground potential before the wordline in the array can be turned off. The low capacitance lines (I/O' and I/O') feed the output buffer circuit and must switch as rapidly as possible. In addition, all nodes must be precharged for both CAS and RAS-only cycles to insure sense amp node equalization. The new circuit in its entirety is shown in the figure. Section A is the precharge circuit for RAS-only operation, to avoid any leakage effects. The precharge clock, OPRE, rises to more than VDD + VT . Section B is the precharge controlled by CAS switching and occurs at the end of any write or read cycle. Thus, both the I/O lines and the I/O' lines are precharged to VDD . Section C is the sense amp which is turned on by the rising edge of øIOL, and Section D is the discharge circuit which is enabled a clock delay later by øIOL'; this circuit is steered by I/O' lines which have undergone full swing by the time øIOL' reaches a threshold voltage. Section E is the isolator circuit for the sense amp which encompasses the new app...