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Recirculation LSSD Loop for AC Testing

IP.com Disclosure Number: IPCOM000043213D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Millham, EH: AUTHOR

Abstract

This article describes a technique for performing AC tests on chips incorporating LSSD circuitry without requiring modifications to existing chip circuitry. Fig. 1 illustrates the conventional recirculating loop. When the CTL input (1) is forced high, the circuit will oscillate at a frequency dependent on the number of circuits in the loop. It should be obvious that an inversion is required for the loop to oscillate. The frequency may be measured at the output (2) using conventional techniques. Fig. 2 shows a conventional shift register latch (SRL) string as used in level sensitive scan device (LSSD) designs. When the clocks (3) are activated in the correct sequence, any logic signal applied to the S1 input (4) will move through the shift register one stage for each clock cycle until finally appearing at the S0 output (5).

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Recirculation LSSD Loop for AC Testing

This article describes a technique for performing AC tests on chips incorporating LSSD circuitry without requiring modifications to existing chip circuitry. Fig. 1 illustrates the conventional recirculating loop. When the CTL input
(1) is forced high, the circuit will oscillate at a frequency dependent on the number of circuits in the loop. It should be obvious that an inversion is required for the loop to oscillate. The frequency may be measured at the output (2) using conventional techniques. Fig. 2 shows a conventional shift register latch (SRL) string as used in level sensitive scan device (LSSD) designs. When the clocks
(3) are activated in the correct sequence, any logic signal applied to the S1 input
(4) will move through the shift register one stage for each clock cycle until finally appearing at the S0 output (5). An interesting concept of SRLs used in LSSD designs is that when the clocks are held to their proper logic state, then any logic signal applied to the S1 will propagate through the entire string to appear at the S0 an increment of time later equal to the sum of the delays through each SRL plus wiring. This is the so-called "flush" test which is used extensively in LSSD testing. By combining the principles of recirculating loop and LSSD flush, it is possible to use the recirculation technique on every chip on a wafer. Fig. 3 illustrates the principle of the LSSD recirculating loop. With the CTL input (6) lo...