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Driver/Receiver Pair for Low Voltage Inverter Circuit

IP.com Disclosure Number: IPCOM000043223D
Original Publication Date: 1984-Jul-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR [+4]

Abstract

This article describes a circuit arrangement which allows communication between chips that use a low voltage inverter (LVI) logic circuit[*]. This pair of circuits provide fast, stable, push-pull off-chip drive with only a 2.1 V supply. The push-pull driver accomplishes five main goals: 1) short delay (<500 ps) Figs. 1A and 1B), 2) good noise margin (280 mV, 3 s worst case), 3) logic capability Fig. 2, 4) zero insertion delay, and 5) stability. The receiver can be regarded as having two parts (see Fig. 2). There is a filter part which converts the large off-chip signal swing to levels which the logic part of the circuit will use. The logic part of the receiver is a LVI circuit. This will allow logic to be perform ed with on-chip signals as well as off-chip signals. Fig. 2 signals OUT 1 and OUT 2).

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Driver/Receiver Pair for Low Voltage Inverter Circuit

This article describes a circuit arrangement which allows communication between chips that use a low voltage inverter (LVI) logic circuit[*]. This pair of circuits provide fast, stable, push-pull off-chip drive with only a 2.1 V supply. The push-pull driver accomplishes five main goals: 1) short delay (<500 ps) Figs. 1A and 1B), 2) good noise margin (280 mV, 3 s worst case), 3) logic capability Fig. 2, 4) zero insertion delay, and 5) stability. The receiver can be regarded as having two parts (see Fig. 2). There is a filter part which converts the large off- chip signal swing to levels which the logic part of the circuit will use. The logic part of the receiver is a LVI circuit. This will allow logic to be perform ed with on- chip signals as well as off-chip signals. Fig. 2 signals OUT 1 and OUT 2). What is being disclosed for the receiver is the use of a filter to limit both the "up" level to LVI as well as the "down" level. If the "up" level is too high, the input will saturate. If the input is too low, the receiver will saturate the input of the next stage. The driver operation is as follows (Fig. 2).

T1A and T1B provide the base inputs for a NOR circuit. T3 has an emitter area four times greater than T2, providing 4X the current in the off-chip driver portion of the circuit. The DK Schottky barrier diode (SBD) protects T3 from excessive current during transient conditions and power supply bring-up. T2A provides a large C-B area which serves two purposes: 1) When the inputs are down, the large C-B junctions of T2 and T2A allow the node B2 to drop below the cut-in of T3. (Simulation has shown that this configuration will keep T3 off for all conditions of power supply, temperature and process statistics. 2) When an input rises, the charge which was stored in the C-B junction of T2 is coupled to the base of T3, transiently turning it on very hard. This gives a very fast down- going output and an excellent capacitive drive ability. RI provides base current when T2 and T3 are conducting. This resistor is the key element in controlling of the down level and power dissipation. Resistor RI is a dumb-bell-type resistor which is formed by the emitter diffusion in a P+ base region. Because of this, the resistor value will track with the bet...