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Process for Transferring Thin-Film Conductor Patterns to a Multilayer Ceramic Substrate for Semiconductor Chips

IP.com Disclosure Number: IPCOM000043234D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Kraus, G: AUTHOR [+3]

Abstract

For providing a multilayer ceramic substrate with additional conductors, which serve as fan-out conductors for the semiconductor chips and which may also be used for repair purposes, the following process steps, illustrated above, are required: Conductor pattern 1 is produced in thin-film technology on a mechanically stable carrier 2. Carrier 2 consists of a low roughness, good planarity material having thermal, mechanical and physical properties similar to those of the multilayer ceramic substrate to which the thin-film structure is finally transferred. It is also essential that the carrier material have a low surface tension which can be achieved by a surface treatment 4, for example, siliconization or a similar treatment.

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Process for Transferring Thin-Film Conductor Patterns to a Multilayer Ceramic Substrate for Semiconductor Chips

For providing a multilayer ceramic substrate with additional conductors, which serve as fan-out conductors for the semiconductor chips and which may also be used for repair purposes, the following process steps, illustrated above, are required: Conductor pattern 1 is produced in thin-film technology on a mechanically stable carrier 2. Carrier 2 consists of a low roughness, good planarity material having thermal, mechanical and physical properties similar to those of the multilayer ceramic substrate to which the thin-film structure is finally transferred. It is also essential that the carrier material have a low surface tension which can be achieved by a surface treatment 4, for example, siliconization or a similar treatment. Suitable carrier materials are, for example, glassy carbon, siliconized glass, fluorinated plastics, such as TEDLAR*, or surface-modified silicon. Subsequently, conductor pattern 1 is generated by known methods on carrier material 2. For non-conductive carriers, a thin metal ground plane 5 is applied which is removed after conductors 1 have been separated from carrier 2. For electrically conductive carriers, conductor pattern l may be generated by electroplating, using a photoresist mask, or by etching a vapor deposited or sputtered metal layer. The bared surface of the conductors 1 is then modified by a surface treatment 6, for exa...