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Deep Double-Implanted LDD for Reducing Substrate Current

IP.com Disclosure Number: IPCOM000043239D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Hsieh, CM: AUTHOR [+3]

Abstract

The Double-Implanted Lightly Doped Drain (DI-LDD) device of [*] improves the FET device characteristics at submicron channel lengths, however, it does not reduce the parasitic N+ - P - N+ gain as devices improve their performance in VLSI technology. Thus, the substrate current will be substantial for high performance circuits. This technique utilizes a deep DI-LDD structure to reduce the substrate current and at the same time preserve the improved device characteristics of the DI-LDD as well. The process sequences are illustrated in Fig. 1: 1. A lightly doped N type impurity is implanted in the source and drain regions prior to gate sidewall growth. 2. The sidewall spacer is formed. 3. P type and N type ions are implanted deeply into the source and drain regions. 4.

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Deep Double-Implanted LDD for Reducing Substrate Current

The Double-Implanted Lightly Doped Drain (DI-LDD) device of [*] improves the FET device characteristics at submicron channel lengths, however, it does not reduce the parasitic N+ - P - N+ gain as devices improve their performance in VLSI technology. Thus, the substrate current will be substantial for high performance circuits. This technique utilizes a deep DI-LDD structure to reduce the substrate current and at the same time preserve the improved device characteristics of the DI-LDD as well. The process sequences are illustrated in Fig. 1: 1. A lightly doped N type impurity is implanted in the source and drain regions prior to gate sidewall

growth.

2. The sidewall spacer is formed.

3. P type and N type ions are implanted deeply into the

source and drain regions.

4. Anneal and drive-in. A P-channel device can be obtained similarly by implanting P-type only in step 3 above instead of two species. Fig. 2 shows the final device structure. The source and drain node to substrate capacitance is almost the same as in the DI-LDD case since the major component of capacitance to substrate is determined by the N+ to field P+ implant capacitance which is identical in both processes. The advantages of the described device are: 1. The parasitic N+ - P - N+ gain of FET devices is reduced to improve the impact ionization, and it has

the same improved device properties as the original

DI-LDD.

2. It is compatible with the CM...